1
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I am beginner in Verilog. So I am confused in coding in Verilog. Can I use one module in another module?

module pn(
  input p,
  input n,
  input clk,
  output reg q
);

  initial begin
    q = 0;
  end

  always @(posedge clk) q=(q&n)|((~q)&p);

endmodule

I want to use it in following module

module ic2323(
  input p0, 
  input n0, 
  input p1, 
  input n1, 
  input clk, 
  output q0, 
  output q1, 
  output x
);

endmodule

Is it possible?

EDIT:

 x=q0~^q1;

this code gives error

Reference to scalar wire 'x' is not a legal reg or variable lvalue

Illegal left hand side of blocking assignment

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2
  • \$\begingroup\$ do you have the x=q0~^q1; inside an always block, or in an assign statement? If it's in an always block, you need to declare reg x first. \$\endgroup\$
    – The Photon
    Commented Apr 7, 2013 at 14:58
  • \$\begingroup\$ yeah, you are right. i noticed problem \$\endgroup\$ Commented Apr 7, 2013 at 15:02

1 Answer 1

3
\$\begingroup\$

Sure, if you couldn't build up a hierarchy, HDLs would be rather limited.

For example, you could have:

module ic2323(
  input p0, 
  input n0, 
  input p1, 
  input n1, 
  input clk, 
  output q0, 
  output q1, 
  output x
);

  // Instantiate a pn for p0, n0 and q0.
  pn pn_a(
    .p   (p0),
    .n   (n0),
    .clk (clk),
    .q   (q0)
  );

  // Instantiate another pn for p1, n1 and q1
  pn pn_b (
    .p   (p1),
    .n   (n1),
    .clk (clk),
    .q   (q1)
  );

  // XNOR the two outputs together
  assign x = ~(q0 ^ q1);

endmodule
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5
  • \$\begingroup\$ when i am doing expression for x, verilog complains that x is legal reg \$\endgroup\$ Commented Apr 7, 2013 at 14:19
  • \$\begingroup\$ x=(pn_a.q)~^(pn_b.q) in this statement \$\endgroup\$ Commented Apr 7, 2013 at 14:26
  • 1
    \$\begingroup\$ You shouldn't refer to the instance ports directly, you need to refer to the signals you've connected to them. For example, assign x = ~q0 ^ q1. \$\endgroup\$
    – Dave Tweed
    Commented Apr 7, 2013 at 14:26
  • \$\begingroup\$ sorry, but it didn't solve problem. when i do as you said, it complains about the same problem \$\endgroup\$ Commented Apr 7, 2013 at 14:36
  • 1
    \$\begingroup\$ You should edit the question to add a followup that shows the complete code for the second module that you're now using, along with the exact error message that the tool is giving you. \$\endgroup\$
    – Dave Tweed
    Commented Apr 7, 2013 at 14:39

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