Which PWR routing strategy has the best return path for a SIG/PWR-GND-GND-SIG/PWR stackup?

Question

I'm trying out the stackup SIG_ROUTE/PWR_ROUTE-GND_PLANE-GND_PLANE-SIG_ROUTE/PWR_ROUTE after reading of its advantages. How should I route power to components on the opposite side of the PCB?

Here is an example PCB. Imagine there is a typical density of digital components on both sides of the PCB, even though most are hidden for simplicity.

Option 1:
Place a via right next to the power source, and route VDD as a star on the other side.

Option 2:
Same as option 1, but add a bulk capacitor on the other side of the PCB.

Option 3:
Route power on the source side to vias close to IC power pins.

Option 4:
Route power to a few "zones", each with its own local bulk cap. Then route to any nearby devices.

Which option provides the best return path through the ground planes?

Any other advice or consideration is welcome.

Answer 1

All options work well. I would go with option 3 (or 1) since:

• Bulk caps from option 4 are not really needed: as long as decoupling caps are sized correctly I don't see a clear benefit to add extra local energy storage.
• Option 1 is OK but if you deal with high currents then the central via might heat. In this case you want to use multiple vias to change layer.
• You won't see any difference between option 1 and 2 (assuming the total bulk cap value is the same) since you don't have to worry about the via inductance (almost only DC on this net).
• Option 3 is cheap

The return path will be from the decoupling caps to the bulk cap on the GND plane just below. As long as the decoupling caps are sufficiently large then this net will see almost only DC. It means the return current will spread on a large portion of the GND plane. The only thing that really matter is the trace width. Design the trace width to handle the current and have a low inductance.

Also you might want to place the GND/(VDD) vias for each chip in such a way that the current is forced to go first into the decoupling cap before reaching the pins. I guess this is important for really high speed chips.

EDIT: according to this link (Routing and placement of decoupling capacitor when using power plane) suggested by comment below, this last point about via placement is wrong!

Answer 2

I assume here the pink/red colour represents bottom SIG/PWR layer whereas dark green/gray is the top SIG/PWR layer. I also assume the part U1 is the power source you talk about.

Routing VDD as a star already makes the path appropriate and I guess in all options return current passes via the GND plane in your design. Placing extra capacitors half way (Option 4) does not make sense: decoupling capacitors should be placed close to the ICs and at the source. Therefore, topology depicted in Option 2 is the most correct.

Selection of the layer (top or bottom) in this example should be decided by whether you can place all the signal routing on the corresponding layer after routing the power.