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I am new to gate driver design. I am designing a Buck-Boost converter and would like to create a gate driver for the MOSFET. I tried simulating TL494 IC on LTspice but there is no PWM signal at the output. The output at the emitter is always high (= 12 V). I plan to drive the gate of a single MOSFET using the TL494 IC. This is my schematic:

enter image description here

These are from the TL494 datasheet:

enter image description here enter image description here

The datasheet can be found here.

My LTspice schematic can be found here with the name pulse_generation_imp.asc .

The spice model of the IC was found here.


Questions:

  • Why can't I get a PWM output at the emitter?
  • I cannot understand the use of two error amplifiers in the IC. It would be very much helpful if someone explained their practical usage in simpler terms. Why are the outputs of the error amplifiers shorted with the feedback input (pin#3)? What does this configuration achieve?
  • Will I be able to generate a PWM signal if I grounded all four pins of the error amplifiers and just give the control signal to the feedback pin (pin# 3). In the schematic, I am able to generate a 100 kHz sawtooth signal that goes from 0 V to 3 V. So, if I use voltages from 0 V to 3 V at pin#3, will I be able to vary the duty cycle of the generated PWM signal at the emitter from 0 to 1? (Without ever needing to use the two error amplifiers)
  • "Normally resistors (apart from RT (pin#6)) are used in the circuit to limit currents entering the IC". Is this statement correct?
  • What does pin#4 (DTC) serve practically? Is there any problem if I ground it? I just need a single PWM output signal to drive the gate of a single MOSFET.
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  • \$\begingroup\$ The error amps act in parallel, wired-OR. Your R3 is probably too large to assert control of the pin. They are used to regulate up to two limiting parameters, usually output voltage and current. If one is unused, the inputs should be tied to VREF and GND -- see application section in datasheet. \$\endgroup\$ Dec 27, 2022 at 14:51
  • \$\begingroup\$ @TimWilliams Thank you. I changed R3 to 1 kilo-ohms. The solver type was also changed to 'alternate'. I can now see a PWM signal at the output. \$\endgroup\$ Dec 27, 2022 at 15:07
  • \$\begingroup\$ Also just now noticing....what the heck is 10k doing in series with VCC?! \$\endgroup\$ Dec 27, 2022 at 17:06
  • \$\begingroup\$ I cannot find the spice model on the link you provided. Can you please update the link? \$\endgroup\$ Dec 27, 2022 at 17:21
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    \$\begingroup\$ Did you try to first replicate the schematic example provided in the datasheet (fig 21)? \$\endgroup\$ Dec 27, 2022 at 17:49

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Following the discussion in the comments, I would like to add a few points:

  • This chip is designed to generate a PWM signal whose duty cycle depends on the difference between the SMPS output voltage setpoint and the measured output voltage
  • The error amplifier is used to compare the difference between the output voltage of the buck-boost and a reference voltage. Ideally this difference is equal to 0, which means the output voltage reached the setpoint
  • You have two error amplifiers for this component which are ORing each other. This is if you want to have two separate feedback networks. The fastest one will be the one which will determine the behaviour of the converter. But my advice is to use just one of them. This is not very common to have two error amplifiers for voltage-control in a PWM chip...

Here the reference voltage Vref (setpoint) is 5V according to the datasheet (pin 14).

If you want to have 10VDC_nom on the output of the buck-boost converter then you need to create a resistive divider bridge to go from 10V to Vref=5V. The output of this divider bridge goes into pin 1, while Vref (pin 14) goes to pin 2 through a resistor.

You then have to place a feedback on the error amplifier. This feedback network (between pin 2 and pin 3) is usually a R-C in series. The values of R and C as well as the values chosen for the resistive divider will impact the dynamic transfer function of the converter. This is called a "compensator network". You will find more detailled information here: https://www.ti.com/lit/an/slva662/slva662.pdf?ts=1672160889532

By doing so, the output of the error amplifier will saturate low while (Vout x G_divider) < Vref. This means the clock of the flip flop will have a low duty cycle, and the duty cycle on the emitter will be high. With a high duty cycle PWM signal for the buck-boost MOSFET, the converter output voltage will increase quickly until (Vout x G_divider) = Vref. At this point the output of the error amplifier stabilizes to a point where the PWM duty cycle reaches the desired value (from the input/output transfer function of the boost converter) and Vout_converter = setpoint.

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