I made the following 1-minute clock circuit in logisim that's supposed to count up to 59 seconds and then loop back to zero:
It works mostly fine, but the problem happens when it reaches 59 and loops back to 0. I've created a small timing diagram below to describe what happens, and as you can see, it ends up spending one extra cycle on zero before it starts counting up again.
I think the problem here comes about because the reset signal for the flip-flops is asynchronous, so it reads in the high input from sec_rollover both at the beginning of the clock cycle and at the end of the clock cycle. My main question here is, what is the "correct" way to design this counter so that it only spends one cycle on each number as intended?
One thing I tried was using logic gates to check if the current number is 60 (instead of 59) and wiring that directly to the flip-flop reset, without anything in between. This works as intended in logisim, but I'm worried that it would cause problems when I try to translate this into a real circuit later on, because it temporarily creates an undefined state where the counter value is both 60 and 0 at the same time.