An SR flip flop is a flip flop that has set and reset inputs like a gated SR latch. How can an SR Flip Flop be made from using a D Flip Flop and other logic gates?

I've done several searches online and nothing really explains this. I believe a latch can determine values based on inputs and/or the clock? And flip flops are dependent on the inputs?

I've sketched several circuits and the SR FF always seems more basic than the D FF.. So I'm confused as to how this can be shown. My book is terrible at explaining things and the questions are basically irrelevant to the explanations in the chapters.

  • \$\begingroup\$ flip-flop and latch are synonyms. \$\endgroup\$
    – Kaz
    Commented Apr 8, 2013 at 2:34
  • \$\begingroup\$ What exactly do you mean by SR FF and D FF. In both cases, are they level-triggered or edge-triggered? The more common idea seems to be that an FF is edge-triggered (the level-triggered thingy being called a latch), but not everyone agrees: the other folks talk about level-triggered flip-flops and edge-triggered flip-flops. For the answer, it makes a big difference. \$\endgroup\$ Commented Apr 8, 2013 at 7:37

4 Answers 4


A D flip flop simply latches the value of a wire on it's D pin at the rising edge of a clock. Using three inputs (S, R, and Q (output of the DFF)), you need to create a small combinational circuit which mimics an SR flop:

  • If S is set, the value of D should be 1
  • If R is set, the value of D should be 0
  • If neither is set, the value of D should be Q

With these three statements it's simple to create a small truth table and from that to create the combinational circuit which should drive your D pin.


You are quite correct that the SR FF is more basic then the D FF. In fact, I expect you would find one or more SR flip-flops inside a D FF. For this reason, I assume doing what you request would only serve as an academic exercise.

Since the main difference here is that the D FF has an added clock, what needs to be done is to generate a clock signal when either button is pressed. (Assuming the inputs are push buttons...the exact implementation will depend on this detail). So, gather together some logic gates to generate the following conditions:

  • A logic term, that will be low when the R button is pressed, and high when the S button is pressed.
  • A clock term, that is normally low, but goes high when either button is pressed.

For completeness, there probably needs to be some delay in the clock term, so that it doesn't change until after the logic term has changed. This can be done by a pair of inverters that don't change the signal, but do delay it.

Of course, if your particular D FF has "preset" and "clear" pins, you may not need to build anything!

  • \$\begingroup\$ Doesn't an SR FF also have a clock (which is what differentiates it from an SR latch)? \$\endgroup\$
    – Tim
    Commented Apr 8, 2013 at 1:41
  • \$\begingroup\$ No, since latch and flip-flop are synonyms, that is a clocked SR latch/flip-flop. \$\endgroup\$
    – Kaz
    Commented Apr 8, 2013 at 2:36
  • \$\begingroup\$ My book makes it sound like latches don't have clocks \$\endgroup\$
    – Justin
    Commented Apr 8, 2013 at 2:59
  • \$\begingroup\$ They don't (especially the SR latch)--that's what made the problem interesting. Since the D FF requires a clock, you have to create one from the input events. \$\endgroup\$
    – gbarry
    Commented Apr 8, 2013 at 4:04

First of all, I think that you need to understand a bunch of concepts in order to answer your question: All digital designers use the name flip-flop for a sequential device that normally samples its inputs and changes its,outputs only at times determined by a clocking signal. On the other hand, most digital designers use the name latch for a sequential device that watches all of its inputs continuously and changes its outputs at any time, independent of a clocking signal. However, 'some textbooks and digital designers may (incorrectly) use the name "flip-flop" for a device that we call a 'latch." In any case, because the functional behaviors of latches and flip-flops are quite different, it is important for the logic designer to know which type is being used in a design, either from the device's part number (e.g., 74x374 vs. 74x373) or from other contextual information.

Regarding to what you have asked, S-R latches are useful in ''control" applications, where we may have independent conditions for setting and resetting a control bit. If the control bit is supposed to be changed only at certain times with respect to a clock signal, then we need an S-R flip-flop that, like a D flip-flop, changes its outputs only on a certain edge of the clock signal. You can get a master/slave S-R flip flop by using two S-R latches. Fig: Master/Slave SR Flip Flop

The logic symbol for the master slave S-R flip- flop does not use a dynamic-input indicator, because the flip-flop is not truly edge triggered. It is more like a latch that follows its input during the entire interval that C is 1 but changes its output to reflect the final latched value only when C goes to 0. In the symbol, a postponed-output indicator indicates that the postponed-output signal does not change until enable input C is negated. Flip-flops with this indicator kind of behavior are sometimes called pulse-triggered flip-flops.

  • \$\begingroup\$ Not all flipflops are clocked \$\endgroup\$ Commented Apr 8, 2013 at 2:00
  • \$\begingroup\$ @ScottSeidman: I have been teached otherwise and that's precisely what I want to clarify in my answer. Latches and Flip Flops do have something in common: they are bistable devices,now, I think a good convention is to call flip flop to the devices that its outputs depends on a clock signal and latches to those who doesn't depend on clock signal. \$\endgroup\$ Commented Apr 8, 2013 at 2:06
  • \$\begingroup\$ Far from universal, though increasingly common. Horowitz and Hill call what you would call a latch an sr flip flop, then go on to talk about clocked flip flops \$\endgroup\$ Commented Apr 8, 2013 at 2:49

An S-R latch can be made from a D flip-flop that has "Set" and "Reset" pins by grounding the clock and data pins. An example chip would be a 74HC74 dual D flip-flop.


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