Another weirdly worded question in my digital logic book. It doesn't specifically define set-dominant or reset-dominant - nor does it show how to use these in practice with drawing circuit diagrams. I've read and reread the chapters and it doesn't specify how to do this..

I did some research online and it appears that NOR SR latches are reset dominant and NAND SR latches are set dominant?

I know that unpredictable behavior happens if S and R inputs are both equal to 1 when the clock changes to a 0. Given a circuit, I'm supposed to create a set dominant gated SR latch in which the conditions S=R=1 causes the latch to be set to 1.

I've included the circuit we're given to start with and my attempt at making it set dominant (don't judge me lol).

Given Circuit: circuit

Characteristic Table: \begin{array}{|c|c|c||c|} clk & S & R & Q(t+1) \\ \hline 0 & X & X & Q(t) \\ 1 & 0 & 0 & Q(t) \\ 1 & 0 & 1 & 0 \\ 1 & 1 & 0 & 1 \\ 1 & 1 & 1 & X \\ \end{array}

My first attempt: attempt

  • \$\begingroup\$ Could you be more clear what is your question? \$\endgroup\$
    – The Photon
    Apr 8 '13 at 3:50
  • \$\begingroup\$ "The gated SR Latch given has unpredictable behavior if the S and R inputs both equal 1 when the Clk changes to 0. One way to solve this is to create a set-dominant gated SR latch in which the conditions S=R=1 causes the latch to be set to 1. Design a set-dominant gated SR latch and show the circuit." Thats what the question says \$\endgroup\$
    – Justin
    Apr 8 '13 at 4:03
  • 1
    \$\begingroup\$ What happens if you re-label R as S and S as R? \$\endgroup\$
    – The Photon
    Apr 8 '13 at 4:16

To rephrase the question: " how do you change the internal operation so that if S*R = 1 that only one of S or R is exerted"

That means you have to put some extra logic in there to control these signals.

Since this is homework and I don't do other's homework, I'll take you through the thought process.

If I want to control S so that when S*R=1 ir generate the control signal S'' = S + SR, S'' = S(1 + R) = S(1) = S so S'' = S so there is no logic to be put in there. Ooops, that clearly is the wrong signal to be playing with.

So that means that you need to block R' signal when S*R = 1. In other words, when S=1 do not allow R' to get to the input of the latch.


I don't have enough reputation to comment.

I googled "reset dominant sr latch" and your definition:

Given a circuit, I'm supposed to create a set dominant gated SR latch in which the conditions S=R=1 causes the latch to be set to 1.

is basically right. I came up with the definition (rephrasing from what I found online):

A reset dominant sr latch is a latch with two data inputs, S and R that has an excitation table similar to an SR latch, except that when both S and R are 1, the next output should be 0 (reset). Set dominant is defined similarly: the next output when S and R are both 1 should be 1 (set).

So you should change the characteristic table so that the "X" in the last row is the proper value ("1" since you've been asked for a "set-dominant" SR latch) and then use whatever plug-n-chug method you've been given to turn a characteristic table into a working circuit.

Your first attempt doesn't work because it gives an undefined next-state when R=S=0, and also enters an undefined state whenever clk is low.

(BTW: AFAIK "Set/Reset dominant" is not standard terminology that would be defined in a text book, it's just a made-up name for the purpose of this particular problem.)

  • \$\begingroup\$ On a typical RS latch, the Q and /Q outputs will be wired such that one is set-dominant and the other is reset-dominant during the time both set and reset are asserted; releasing set and reset simultaneously will yield undefined behavior. One could also design a circuit so that set was level-activated and dominant but reset was edge triggered. In that case, behavior would be deterministic in all cases except where the inactive edge on set coincided with the active edge on reset. \$\endgroup\$
    – supercat
    Jun 7 '13 at 17:21

Design Modification

When both AND gates are enabled (CLK = 1), the only modification is R' = S̅ R in the top AND gate with S' = S left unchaged in the bottom AND gate. As shown below, the following circuit will convert the given circuit from set/reset neutral to set dominant latch. All we did was feeding an extra S̅ signal through an inverter to the top AND gate.

Rationale for feeding an extra S̅ signal through an inverter to the top AND gate

Consider R = S = 1 we have R' =1 and S' = 1 which causes the latch to be unpredictable in the original circuit. Now we have R' = 0 and S' = 1 which sets the latch in the new design as required.

Next we want to make sure we are preserving the operations in all other cases. For the cases R = 0, S = 0 (Hold) or R = 1, S = 0 (Reset), their operations are not affected by the modification as S = 0 will cause S̅ to be set (or S̅ = 1). S̅ = 1, in turn, plays the role of enabling the top AND gate and nothing else. The only case left is R = 0, S = 1 (Set). The modification has no effect on the top AND gate either as R = 0 resets it to 0 anyway regardless of whether S̅ is present.

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