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See for example this code: I want that if counter is not equal to 40, it should increment by 40 or when it is 40, it should be zero.

I know I can place that increment statement in the else block.

If I want to maintain program simplicity or want to divide it into different sections, is there any other way or keyword in Verilog through which I can mean "please let the previous assignment in the same block take effect"?

module jdoodle;
reg [15:0] counter;
reg clk;
initial begin
    counter <= 0;
    clk <= 0;
    $monitor("counter = %b %d", counter, counter);
    #2500;
    $finish;
end

initial forever #5 clk <= ~clk;

always @ (posedge clk) begin
    counter <= counter + 40;
    if (counter == 40) begin
        counter <= 0;
    end else begin
        counter <= counter; // This basically lets counter only have its initial value which is "0" from initial block.
                            // and never increment.
    end
end 
endmodule
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2 Answers 2

2
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What you are looking for is called "default assignment". If there are multiple assignments to the same entity within an always block, the last one in source-code sequence is the one that is used. For example:

  always @(posedge clock) begin
    counter <= counter + 1;          /* default assignment */
    if (counter == 40) counter <= 0; /* overrides default when counter is 40 */
  end

This sort of thing is frequently seen in larger state machines constructed with case statements. All outputs get a default assignment ahead of the case statement, so that the individual cases only need to contain the non-default values, which makes the whole thing easier to read.

There is no separate keyword for this. But it's a good idea to clearly document default assignments in the comments.

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5
  • \$\begingroup\$ The reason behind asking this question is: Is it necessary to have an else statement for every if statement in verilog like we have default statement for a case in verilog? My professor says that you should always terminate an if statement with an else block, but if I want to write it as else: do nothing or pass I can do it in "python", I don't find a similar way in verilog which is translatable to digital design. \$\endgroup\$
    – lousycoder
    Jan 1, 2023 at 16:18
  • \$\begingroup\$ Your professor's statement is not a technical language requirement, but rather his idea of "good coding practice". It's actually not a bad idea, especially if other coders of unknown skill level are going to be looking at the code. It also helps with avoiding the creation of implied latches. But if you really want "else do nothing", then just leave the else part off altogether, as I did above. \$\endgroup\$
    – Dave Tweed
    Jan 1, 2023 at 17:11
  • \$\begingroup\$ Ok, if I were to follow what you just did, how do I make sure that I am avoiding implied latch creation? \$\endgroup\$
    – lousycoder
    Jan 1, 2023 at 18:47
  • 1
    \$\begingroup\$ @lousycoder Code that starts with always @(posedge clk) never creates latches. It will instantiate sequential registers for any variable you write to inside the block that is read outside the block. Also, any variable you read before writing to in the block. \$\endgroup\$
    – dave_59
    Jan 2, 2023 at 6:56
  • \$\begingroup\$ @dave_59 Probably I'm coming across this fact for the first time. Alternatively, by "latch", I'm here referring to creation of a memory element which implicitly tries to remember previous assignment. \$\endgroup\$
    – lousycoder
    Jan 2, 2023 at 18:06
1
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You just need to change your always block to the following:

always @ (posedge clk) begin
    if (counter == 40) begin
        counter <= 0;
    end else begin
        counter <= counter + 1;
    end
end 

The count starts at 0 and increments by 1 on every clock cycle. When it reaches 40, the count resets to 0, then increments by 1 again, etc.

Since you only count from 0 to 40, there is no need for the count to be 16 bits (6 bits will do).

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1
  • \$\begingroup\$ As expressed in the question description, I know this solution is possible. Is there any other keyword or a way to do what I'm referring to? When different if blocks are changing one variable based on different conditions which are further apart in a big code? \$\endgroup\$
    – lousycoder
    Jan 1, 2023 at 12:09

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