I'm a novice when it comes to digital audio. What's the best way to convert 48 kHz I2S to 44.1 kHz? I have found the Texas Instruments SRC4392 but I do not believe that it will work for this application.

I have a Bluetooth module that outputs audio between 44.1 kHz and 48 kHz depending, and I need to convert the output I2S to S/PDIF @ 44.1 kHz consistently.

  • 2
    \$\begingroup\$ If you have an MCU with a few spare MHz available, I would do it in software whenever you're moving the data between the chip interfaces. If it is all hardware with no MCU, you'd have to add something. Lots of papers on efficient audio resampling, but I'm partial to cubic hermite resampling since its pretty good and very CPU efficient. \$\endgroup\$ Jan 3, 2023 at 18:55
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    \$\begingroup\$ Does the Bluetooth module feed a processor? How capable is the processor? Sample rate conversion is a well-established technique, so assuming you have enough processing power you could do it on-board. \$\endgroup\$
    – TimWescott
    Jan 3, 2023 at 18:55
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    \$\begingroup\$ Why wouldn't the SRC4392 work? It's designed for exactly this application. \$\endgroup\$ Jan 3, 2023 at 18:56
  • \$\begingroup\$ @user1850479 The MCU I have doesn't have the free I/O pins to do this :( \$\endgroup\$
    – t3ddftw
    Jan 3, 2023 at 19:21
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    \$\begingroup\$ Well, it sounds like your hardware is inadequate to the task, then. So the best thing to do is either find a BT module that lets you run code on it, or put a microcontroller on the board and put it in charge. \$\endgroup\$
    – TimWescott
    Jan 3, 2023 at 20:55

1 Answer 1


Look at page 4 of the SRC4392 datasheet. It explicitly lists a dynamic range specification for the sample rate converter at "f(in) : f(out) = 48kHz : 44.1kHz". So it definitely supports this particular conversion.

The sample rate converter in the SRC4392 can operate with asynchronous input and output clocks. This means that the receiver circuitry ("DIR" or Port A/B) can operate with a different sampling clock frequency than the transmitter ("DIT").

Additionally, the receiver circuitry can do clock recovery from the received audio stream. This means that its reference clock does not have to be a multiple of the received data rate.

So, to configure the SRC4392 properly for 48kHz to 44.1kHz conversion, you have to do the following:

  • Apply a suitable multiple of 44.1kHz to the MCLK input (master clock, likely 22.5792MHz, which is 512*44.1kHz)
  • Configure the DIT (transmitter) to operate from MCLK and accept data from the SRC (sample rate converter)
  • Configure the SRC to operate from MCLK as well
  • Configure the SRC to accept input data from one of the audio input ports (Port A or Port B)

The chip will then feed two different sampling frequencies (the 48kHz input reference clock from port A/B, and the MCLK-derived 44.1kHz output reference clock) into the sample rate converter. The converter's rate estimator will automatically select the proper resampling parameters for 48kHz to 44.1kHz sample rate conversion.

Note that the chip's operation is completely independent of the input sampling rate when configured like this, so it'll still work even if the input sampling rate changes. It'll just convert any sampling rate you throw at it to 44.1kHz.

Also, the receiver's PLL is only needed to generate a clock frequency that's much higher than the input data rate so that it can oversample the input signal and do clock recovery. This is what allows it to operate with a clock that's asynchronous to the input data stream. The PLL output clock doesn't have to be an integer multiple of the input data rate, it just has to be high enough for the oversampling scheme to work. An integer multiple clock frequency (i.e. 512x) is only needed for the transmitter.


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