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I am tinkering with a device to generate pulses for a measurement setup. No need to buy it: Just wondering how one would implement it.

Idea:

Device generates a square-wave (Vpp and DC-offset) output between V- and V+ with frequency f, duty-cycle d, and rise = fall times of t.

Requirements:

Vout: -5V <= V- and V+ <= +5V, adjustable via DAC (Vpp and offset)

Frequency: 10 Hz<->1 MHz with 1 Hz resolution and low jitter (Maybe via uC timer?)

Duty-cycle between 10 and 90% (maybe via uC timer?)

tRise/tFall adjustable between 1 ns and 10 ms (Yes, 10 ms for the low frequencies). The rise/fall portion of the square wave should be fairly linear.

The operations are somewhat simple: Set offset and Vpp, set f/d/tRise/tFall and generate a pulse-train for example. Or a continuous signal if you like.

My ideas:

I get my head around the output-stage: Feed the "finished" (correct wave form, normalized amplitude and DC offset) into a analog-stage which adds DC offset and scaling based on DAC outputs. Feed it into 50 Ω BNC. So far so good.

I also can get my head around how to generate the variable signal (control frequency and duty cycle) via an uC timer for example.

What I can not get: How to make the rise/fall times controllable in some way? I mean, you could oversample the signal with a DAC pretty hard -> let's say 100 MSamples would allow to "approximate the ramp" in 100 steps. But there have to be different ways to do this, which I can't come up with.

Question:

How could one implement this without oversampling/approximating the waveform with a really fast DAC?

Are there some op-amps out there which give you configurable (e.g. via analog-input) slew-rates? Or are there logic gates which can do this? Are there any parts (especially over the entire range 1 ns<->10 ms)?

I mean you could also use a good ARB and build "parametric-waveforms" of some sort, but this goes down the "sample a DAC really fast" road.

Edit 1:

Based on user4474's input I came up with this idea:

schematic

simulate this circuit – Schematic created using CircuitLab

This should give a output voltage which swings between V-<->V+ with "controllable" ramp rates based on the DAC bias voltages. The actual signal is generated via PWM and can be fed into the switches connecting the DAC voltages to the circuit.

Then, based on four switches, the desired signal is derived and can bee feed into the scale and offset stage.

Edit 2:

Based on Kuba hasn't forgotten Monica answer i drew up a shematic. enter image description here

A variable amount of current is forced thorugh a integration capacitor C_i. Therefore a speific voltage is across the voltage based on the time and the amount of current used. The Ramp can therefore be controlled by controlling the current thorugh the cap. This voltage is buffered and scaled / Dc-offset and pushed into the output.

To limit transient effects when switching current sources, they pump their current into an op-amp at the same voltage as the integrator cap if not in use. For switching one could use Make-Before-Break Analog switches. The voltage accross the integrator is limited to a given threshold with two op-amps (positive and negative clamp).

The raw PWM signal can be used to manipulate the current soure switches, while the "ramp-rate" can be controlled by a I(u) source of some sort (DAC with Op-Amp).

Rising/Falling Edges can be achieved by sourcing/sinking positive/negative current "into" the C respectivly.

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    \$\begingroup\$ The 1ns spec is going to make this a lot harder to build. Going from -5V to +5V in 1ns means the op-amp at the output stage has to have a slew rate of 10,000,000,000 V/s. I would be surprised if you could find any op-amp with those specs. Also, the ratio between 10ms and 1ns is like 10,000,000. So, you would need the digital part that sets the ramp rate to have at least 24 bits of resolution. For PWM forget it. Using a DAC possibly. \$\endgroup\$
    – user4574
    Commented Jan 3, 2023 at 23:24
  • \$\begingroup\$ It might make sense to segment this design into two generators. One that goes from like 10Hz to 10kHz, and another that goes from 10kHz to 10MHz. That would make each section only need 1000:1 range on the timing (which can be done with 10 bits of resolution). You can then use a telecom relay to pick which output you want. \$\endgroup\$
    – user4574
    Commented Jan 3, 2023 at 23:27
  • \$\begingroup\$ How much resolution do you need on the rise time adjustment? Do you need to be able to pick hundreds or thousands of values, or is having like 10 options sufficient? \$\endgroup\$
    – user4574
    Commented Jan 3, 2023 at 23:39
  • \$\begingroup\$ @user4574 Thank you for your input. Slew-Rate seems to be a big Issue - Didnt think of that. Then lets limit the design to 500MV/s - there should be parts available. Okay: Then the architekture you recommend is somewhat like this: Generate "unified" PWM square-wave signal (10Hz<.>1MHz) by uC (Different Clock-Sources for Timer and different Prescalers to get the resolution with range switching) -> Scale Signal -> Apply DC Offset -> Buffer -> Output What i mean by Clock Switching: External 10MHz ClkRef -> 8Bit Timer -> Event feeds 16bit Timer for PWM. \$\endgroup\$ Commented Jan 4, 2023 at 0:02
  • \$\begingroup\$ Regarding the idea of using a really fast DAC: Getting a DAC that operates a couple hundred MHz isn't impossible, but the DAC chip itself will be expensive, and you will either need higher end MCU/processor or an FPGA to feed it data fast enough. \$\endgroup\$
    – user4574
    Commented Jan 4, 2023 at 0:34

2 Answers 2

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Fast pulse generators with controllable slew rates typically use current sources, current switches, and clamps.

The diagram below illustrates the key parts of one design for such a generator:

schematic

simulate this circuit – Schematic created using CircuitLab

The "central" component is the integrating capacitor C1. Rising- and falling ramps are generated by connecting one of two current sources to the capacitor. High and low output levels are established by clamps that act as ideal diodes.

When the current sources are not used to charge or discharge the integrator, they are "parked", or bootstrapped, to the integrator potential. This minimizes the transients, as the current source output voltages don't need to slew when they transfer from the parking node to capacitor node.

In practical implementations, the high-current sources used for fast slew rate range and low-current sources used for long ramps usually end up separate, since their circuitry has to be optimized for speed and precision, respectively.

The current-source switches need relatively low charge injection - matched bipolar transistor pairs usually excel at this task. The parking/bootstrap buffer needs to be a fast voltage follower, with offset trimmed to zero. The output buffer can have selectable gain, per desired output voltage range.

There are various designs possible for the clamps, with their own trade-offs. One possible implementation uses a fast comparator to "shut down" the current source (redirect it to the parking/bootstrap node).

schematic

simulate this circuit

The idealized output voltage and switch control waveforms are shown below.

Switch voltage and switch control waveforms

Old school 1-2ns comparators can be made with an avalanche threshold detector with a pulse output using e.g. 2N2904, appropriately biased, and a pulse stretcher (see e.g. Linear Technology AN72, page 34).

There are modern comparators that propagate on the order of 1ns, and those would be easier to apply here.

We could start implementing this idea with more realistic current switches:

schematic

simulate this circuit

The performance is similar to our initial model:

The ramp and current control waveforms of the first implementation

Now we can implement the bootstrap buffer:

schematic

simulate this circuit

Q5-Q8 cascode the current sources and bootstrap the collectors to a roughly fixed potential.

Since the current sources are double-cascoded, the emitter potentials of the current switches are quite stable, and an unsophisticated low-frequency op-amp based current source can be used.

schematic

simulate this circuit

The performance is still reasonable for how simple the circuit is so far:

The ramp and current control waveforms of the third implementation

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  • \$\begingroup\$ Thank you very much for your response. If i understand this correctly, a variable amount (different sources in some combination) of current is forced through a capacitor U = Q/C = 1/C*int(i)dt. The Voltage is clamped by providing a low impedance "sink" which allows the current to flow after a certain threshold is crossed. To limit "transient effects" on the current sources, they are kept at the current Capacitor-Voltage all time, but dump their current somewhere else, if they are not currently used to charge the cap. The voltage across the cap is buffered and scaled to feed it into the output. \$\endgroup\$ Commented Jan 5, 2023 at 0:11
  • \$\begingroup\$ I guess there could be advantages to this, as the capacitor tolerance/current tolerance will cancel out if used for charging and discharging with fixed amounts of time - somewhat like in a Multi-Slope integrator ADC. Correct or do you have any information on this at hand? \$\endgroup\$ Commented Jan 5, 2023 at 0:14
  • \$\begingroup\$ I can also see, that the charge injection caused by analog switches is less of a deal compared to an "voltage-driven" node als i can be dumped into the C with lower effect, than dumping it into a high impedance OpAmp input node. Correct or do you have any information on this at hand? \$\endgroup\$ Commented Jan 5, 2023 at 0:16
  • \$\begingroup\$ I added an Edit to my original post - mind having a look? I find your design quite novel tbh. \$\endgroup\$ Commented Jan 5, 2023 at 0:41
  • \$\begingroup\$ @ElectronicsStudent "My" design is a paraphrase of the patterns typically seen in professional pulse generators. It's not novel in absolute terms :) \$\endgroup\$ Commented Jan 5, 2023 at 0:48
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You can create a controlled ramp rate by feeding an integrator circuit with a DAC output.

I would suggest segmenting this design into two generators. One that goes from like 10Hz to 10kHz, and another that goes from 10kHz to 10MHz. That would make each section only need 1000:1 range on the timing (which can be done with 10 bits of resolution). You can then use a telecom relay to pick which output you want.

schematic

simulate this circuit – Schematic created using CircuitLab

The circuit shown will ramp towards +5V or -5V with a variable rate depending on the DAC output. I relaxed the 1ns rise time to 10ns otherwise there would likely be zero chance of finding an op amp that could meet the timing requirements.

The capacitors should be NP0 type for high stability and good frequency characteristics.

The precise slew rate in V/s on the op-amp output is...

$$SLEW = \frac{-DAC_{VOUT}}{R*C}$$

For the fast side its...

$$SLEW = -DAC_{VOUT}*212MV/s$$

For the slow side its...

$$SLEW = -DAC_{VOUT}*200kV/s$$

The slew out signal should then feed into your gain and offset circuit. You could also put the gain and offset before the relay so you could use different parts for the high and low frequency sides.

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  • \$\begingroup\$ Thank you for your response. Do i understand this correctly? If I set DAC-CH1 to +5V it ramps from 0->5V faster then if is set it to lets say 1V -> hereby providing a positive edge. And after a delay (suiting my frequency and duty cycle requirements) i set it to -x so it ramps with dU(VDAC) towards -5V? If so: It should be easy to generate only a 0<->V+ signal with acontrolled Rise/Fall times which is then scaled and offset to -5<->+5V according to the settings -correct? (Just Power OpAmp from GND<->V+) \$\endgroup\$ Commented Jan 4, 2023 at 0:08
  • \$\begingroup\$ Also the Source-Selection for the following Gain+Offset+Buffer Sections could be done by an analog switch i guess. Would introduce a RC-Filter between Switch and Next-Stage tough. Or is the Relay used for any special reason over a analog-switch? \$\endgroup\$ Commented Jan 4, 2023 at 0:11
  • \$\begingroup\$ @ElectronicsStudent Using a relay is going to offer much higher performance compared to an analog switch. Analog switches are almost always based on MOSFETs which have many pF of stray capacitance. Even a few 10s of pF of stray capacitance is going to make it a lot harder for the op-amp to drive the output. If choosing an analog switch be very mindful of the input/output capacitance values listed in the datasheet. \$\endgroup\$
    – user4574
    Commented Jan 4, 2023 at 0:14
  • \$\begingroup\$ @ElectronicsStudent Your interpretation is mostly correct regarding the slew rate. The integrators are inverting. Setting the DAC negative causes, the output to ramp to +5V. Setting it positive causes the output to ramp towards -5V. A 5V setting is full speed. A 1V setting is 20% of full speed, etc. If it's easier for some reason, you could make this without a -5V supply on the DAC/op-amps by connecting the + input of the op-amp to a 2.5V reference. In that case you get an output between 0V and 5V. \$\endgroup\$
    – user4574
    Commented Jan 4, 2023 at 0:18
  • \$\begingroup\$ I added an Edit to the original Post - mind taking a look? Thank you! \$\endgroup\$ Commented Jan 4, 2023 at 15:17

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