How tightly should trace lengths be matched for a 1Gbps serial databus? It seems to me that 100ps (15mm) should be more than sufficient. However:

The Raspberry Pi Computer Module 4 (CM4) datasheet states:

2.7. CSI-2 (MIPI serial camera): The CM4 supports two camera ports: CAM0 (2 lanes) and CAM1 (4 lanes). CSI signals should be routed as 100Ω differential pairs. Each signal within a pair should ideally be matched to better than 0.15mm.

2.8. DSI (MIPI serial display): The CM4 supports two display ports: DISP0 (2 lanes) and DISP1 (4 lanes). Each lane supports a maximum data rate per lane of 1Gbps...DSI signals should be routed as 100Ω differential pairs; each signal within a pair should ideally be matched to better than 0.15mm.

The CM4 DSI interface is 1Gbps (per lane, and presumably so is the CSI interface). However, the suggested length matching is 0.15mm (1 picosecond!). Why do we need 1ps matching for signals where a clock cycle is 1000 times longer! Is this recommendation a mistake? Overly conservative?

What is the general rule for length matching 1Gbps signals?

  • \$\begingroup\$ The clock rate of 1Gbps is likely not the reason. Please note it says within a pair so that is a hint, because it does not say between the pairs. What is the rise time of DSI signal? \$\endgroup\$
    – Justme
    Jan 3, 2023 at 19:38

1 Answer 1


It is a common misconception that you are length matching for a specific frequency or clock rate. The digital signal has a defined rise/fall time and length matching has to be done so that the rising or falling edges arrive within a specified time interval, so that the receiver can accurately detect the crossing of the differential signals.

While most commonly it is referred to as "length matching" and most datasheets and application notes offer the matching length, the traces are actually matched for signal propagation time so that the rising/falling edges arrive at the receiver at the same time.

In your case, the datasheet has explicitly defined the length to which you should match the signal lines. Please note that the signal propagation time on the outer layer and within the inner layer is not the same. This means that when routing the signals, you should take care that lengths match within a layer.

If you would like to know more, I found the answer to this same question a year ago from this great presentation by Rick Hartley: What your Differential Pairs Wish You Knew (at 11:30 Rick is starting to talk about rise/fall times vs frequency and at 47:23 you can see a table where he compared signal frequency vs skew or the timing difference to which you have to match the signal lines).

  • \$\begingroup\$ The Rick Hartley presentation is a wonderful resource. Thanks for sharing! This should be required viewing for all PCB designers. \$\endgroup\$
    – Mike
    Jan 4, 2023 at 0:22
  • \$\begingroup\$ Glad I could help and I totally agree with you. The presentation and materials shared by Rick Hartley, Eric Bogatin and Robert Feranec have helped immensely while I was learning PCB design. \$\endgroup\$ Jan 4, 2023 at 9:02

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