I'm reading an reference design app note for the STM32 F10xxxx family MCUs. Regarding decoupling caps for the VDD pins, it says:

6.4 Decoupling

In addition, each power supply pair must be decoupled with filtering ceramic capacitors C (100 nF) and a chemical capacitor C of about 10 μF connected in parallel on the STM32F10xxx device. [...] Figure 13 shows the typical layout of such a VDD/VSS pair.


However, the schematic in the same document just 3 pages later, looks like this:



These are contradictory. The PCB layout diagram is showing that you need to pair each VDD_n / VSS_n with a decoupling cap. But the schematic is showing that all the VDDs should be tied together and connected to the power supply plane, and all the VSSs tied together and connected to the GND plane, with decoupling caps off somewhere else decoupling between those two planes.

Which should I follow?

(Side note: even if I follow the PCB layout recommendation, all of the VDDs are ultimately going to need to be tied together to accommodate the single 10uF (C17) bulk capacitor. So, I wonder if there is even any point in even trying to follow the PCB layout recommendation...)

  • 8
    \$\begingroup\$ they are not contradictory ... a schematic diagram does not contain layout information ... you would not put all of the decoupling capacitors in one corner of the PCB just because the schematic diagram clumps them together \$\endgroup\$
    – jsotola
    Commented Jan 8, 2023 at 4:10

2 Answers 2


You should absolutely follow the layout guidelines.

Schematic diagrams are often drawn to make the circuit easy to understand. For this reason, you will see that pin-out of components does not always match the physical position/order.

In the case of decoupling, as you say, all the nets are tied together in the end, so it does not matter where the caps are placed on the schematic. If you were to place each pair of caps next to the pins and connect them with nets, I would bet that the schematic would end up messier and harder to read. Personally, I prefer the middle ground:

enter image description here

The whole reason why you have the layout guidelines, is because the schematics by themselves do not convey this critical information. Sometimes, the designers put this info directly in the schematics in form of notes.

enter image description here

  • 1
    \$\begingroup\$ "I prefer the middle ground". Absolutely, in the example you give just there it is very clear that these are decoupling capacitors, and which bank of pins they are intended to decouple (rather than just being general decoupling, or decoupling for a different device) \$\endgroup\$
    – Rodney
    Commented Jan 9, 2023 at 0:52

They are not contradictory. That is just a way of drawing bypass caps in a schematic.

Always follow the PCB design guide, but since in the end, the supply nodes are still all called VCC and GND so there are multiple ways to draw the same connections in schematics.

The schematic and PCB designs do match, but they are different views of the same design.

A schematic is like a block diagram which detailedly describes what components there are how they are wired logically together.

The PCB design is a physical implementation of the schematics, you can place the components and make wirings between them as you see fit.

In this case, the schematic designer has drawn bypass caps between supply and ground pins. They are just drawn further away to have a separate section where all bypass caps are, in order to have less random wiring near the MCU.

It is then the PCB designer, maybe same person as schematic designer, who needs to know that those caps must be drawn right next to MCU supply pin pairs and any other details how to wire them.

It is actually very clear that which caps in the schematic are supposed to be near which pins, sometimes no wire is drawn from caps to supply pin, and caps are even further away.

Sometimes schematic designers put notes on the schematic to inform PCB designer how to wire them. The bypass caps is just one example. Another example is that a pair of signals should be routed as a differential pair with certain impedance.


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