I'm reading an reference design app note for the STM32 F10xxxx family MCUs. Regarding decoupling caps for the VDD pins, it says:
In addition, each power supply pair must be decoupled with filtering ceramic capacitors C (100 nF) and a chemical capacitor C of about 10 μF connected in parallel on the STM32F10xxx device. [...] Figure 13 shows the typical layout of such a VDD/VSS pair.
However, the schematic in the same document just 3 pages later, looks like this:
These are contradictory. The PCB layout diagram is showing that you need to pair each VDD_n / VSS_n with a decoupling cap. But the schematic is showing that all the VDDs should be tied together and connected to the power supply plane, and all the VSSs tied together and connected to the GND plane, with decoupling caps off somewhere else decoupling between those two planes.
Which should I follow?
(Side note: even if I follow the PCB layout recommendation, all of the VDDs are ultimately going to need to be tied together to accommodate the single 10uF (C17) bulk capacitor. So, I wonder if there is even any point in even trying to follow the PCB layout recommendation...)