# How to determine the phase margin when the Bode plot never crosses 0 dB?

I have a graph that looks like this. I am tasked to measure the phase margin, but the graph doesn't exceed 0 dB.

The circuit is this. The input DC level is 0.6 V, which is the problem. When I change the input DC level, the graph becomes more reasonable. But I need it to be 0.6 V.

What to say about the phase margin in this situation?

UPDATE

I am allowed to change input DC level now, and changed it to 0.55 V. Output DC level is 0.15 V. I measured the phase margin as ~171°.

Update 2: Further investigation of the circuit

Circuit with an inductor connected between Vin and Vout:

Its bode plot:

Circuit with a capacitor before the input:

Its bode plot:

• What do you mean the input DC level "should be" 0.6 V. Were you assigned to design an amplifier that works with that DC level? Or did someone claim it was at that level for a similar circuit? or ... ? Simply put, this isn't an amplifier when operated at that bias point, so there's no need to worry about stability, and no need to worry about phase margin. Commented Jan 8, 2023 at 23:29
• Are you allowed to provide a negative supply for the source terminals of the NMOS? Commented Jan 8, 2023 at 23:29
• Please annotate bias points Commented Jan 9, 2023 at 5:55
• You must always verify the operating bias points before considering results from a .AC analysis. In your case, as highlighted by ErnestoG, please check what is the dc bias on the $V_{out}$ node and make sure it is within an acceptable range and not railed up to $V_{DD}$ or ground. Considering a 1.8-V $V_{DD}$, 1 V or so would probably be a meaningful level. Commented Jan 9, 2023 at 12:17
• Thank you all for the answers! I edited my question and included bias points. My problem is solved by changing the input DC level. I had to stick to 0.6 volts then. Still, I have no idea why a 50 mV shift changes the frequency response this much, but thank you all for your time! I'm gonna connect some capacitors now. Commented Jan 10, 2023 at 21:27

You're forgetting something crucial: the biasing of your amplifier input and output.

If you want to test open-loop gain, it is important that your input and output remain at a well-defined DC voltage.

Something very simple you can do is put a very large inductor (1T H, for example) connecting your input and output. In this way, both input and output will be biased at the same DC level, while being disconnected at AC frequency (because the inductor is, basically, an open at higher frequencies).

You can feed an AC 1 voltage source from the input through a very large capacitor as well (You could do 1T F). This has the opposite function as the inductor; it will behave as a short at AC frequencies (which is what you want to feed the amplifier), while being an open at DC in order to not disturb the DC biasing.

In this way, you can then plot vout/vin and get the open-loop gain you're looking for.

• Hi! I followed your advices, tried some different DC values, but I still get weird bode plots. Seems like the only optimal DC input value for this circuit is 0.55 V. Which is weird for a textbook problem to be this dependent on dc input level. Commented Jan 20, 2023 at 22:38
• Thank you genuinely for the insights, I really appreciate Commented Jan 20, 2023 at 22:39
• But that's the problem, there are no "values to try". Simply connect the amplifier as I indicated, check that the input and output voltages are the same (and hopefully, close to Vdd/2) and then show the open loop response. Commented Jan 20, 2023 at 22:43