How to determine the phase margin when the Bode plot never crosses 0 dB?

Question

I have a graph that looks like this. I am tasked to measure the phase margin, but the graph doesn't exceed 0 dB.

The circuit is this. The input DC level is 0.6 V, which is the problem. When I change the input DC level, the graph becomes more reasonable. But I need it to be 0.6 V.

What to say about the phase margin in this situation?

UPDATE

I am allowed to change input DC level now, and changed it to 0.55 V. Output DC level is 0.15 V. I measured the phase margin as ~171°.

Update 2: Further investigation of the circuit

Circuit with an inductor connected between Vin and Vout:

Its bode plot:

Circuit with a capacitor before the input:

Its bode plot:

Answer 1

You're forgetting something crucial: the biasing of your amplifier input and output.

If you want to test open-loop gain, it is important that your input and output remain at a well-defined DC voltage.

Something very simple you can do is put a very large inductor (1T H, for example) connecting your input and output. In this way, both input and output will be biased at the same DC level, while being disconnected at AC frequency (because the inductor is, basically, an open at higher frequencies).

You can feed an AC 1 voltage source from the input through a very large capacitor as well (You could do 1T F). This has the opposite function as the inductor; it will behave as a short at AC frequencies (which is what you want to feed the amplifier), while being an open at DC in order to not disturb the DC biasing.

In this way, you can then plot vout/vin and get the open-loop gain you're looking for.