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Precharging sets the bit line voltage is set to Vdd/2. To read from a dynamic memory cell, the bit line voltage must be near Vdd/2 for the sense amplifier to amplify the data value correctly. Since the bit line acts as a capacitor, its voltage will drop over time.

Why, then, do DRAM state machines mandate the commands to follow the ACTIVATE -> READ/WRITE -> PRECHARGE pattern? The time between a precharge and activate command could be very long (8x tREFI in DDR SDRAM) -- would the bit line voltage not drop far below Vdd/2 in this time?

To me, it would make sense to first precharge the bitline, then read the data from the memory array and into the sense amplifiers. I don't see how a precharge is necessary after a cell's data has already been read.

Why is the precharge command mandated after a read operation is completed?

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  • \$\begingroup\$ That doesn't answer my question. I know what precharge is, I even explain it in my post. I am asking why the DRAM state machine requests a precharge at the end of a read cycle (and not at the beginning). The OP under that post asked the same question I did, but got no response. \$\endgroup\$
    – jayded-bee
    Commented Jan 8, 2023 at 23:47
  • \$\begingroup\$ My knowledge around DRAM internals is a bit too rusty to give you a confident answer, but I do have a few notes based on my understanding: It's the row line rather than the bit line that gets charged. There's very little DC leakage current from the row line, in part because the attached FETs' Vgs and Vds aren't changing, so there's no capacitive divider effect from the Cgd/Cgs and everything kinda sits in a steady state. Any charge leakage from the row line is part of the minimum refresh period calculation. \$\endgroup\$
    – Polynomial
    Commented Jan 9, 2023 at 4:02
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    \$\begingroup\$ If you refreshed first, then read, there'd be a greater latency to the first byte read, since you'd have to wait for the precharge rather than it already being done after your last read. Doing it afterwards also permits features like auto-precharge after tRAS. Speculating a little: if you precharged first, then left the row line at 0V or Vdd after a read, then the magnitude of leakage from the cells to the row line would be heavily reduced for cells at the same potential, but increased for cells at the opposing potential, so that'd almost certainly force a shorter refresh period. \$\endgroup\$
    – Polynomial
    Commented Jan 9, 2023 at 4:06
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    \$\begingroup\$ Sorry, yes, it is the bitline not the wordline. I was misremembering. \$\endgroup\$
    – Polynomial
    Commented Jan 11, 2023 at 23:34
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    \$\begingroup\$ I've formatted my comment as an answer. It's possible that someone will come by later and provide more details. \$\endgroup\$
    – Polynomial
    Commented Jan 16, 2023 at 16:07

1 Answer 1

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If you refreshed first, then read, there'd be a greater latency to the first byte read, since you'd have to wait for the precharge rather than it already being done after your last read. Doing it afterwards also permits features like auto-precharge after tRAS.

I'm not 100% sure, but to speculate a little: if you precharged first, then left the row line at 0V or Vdd after a read, then the magnitude of leakage from the cells to the bit line would be reduced for cells at the same potential, but increased for cells at the opposing potential, so that'd almost certainly force a shorter refresh period.

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