Based on my rough analysis, I realized that by measuring a thermistor in a Wheatstone configuration, I could technically reduce the ADC offset error LSBs because we are substracting two divider voltages.
This subtraction should eliminate the ADC offset error term and should allow me to use a much lower-cost ADC. However, I don't see anyone discussing it nor any Google search result talking about it.
I am wondering if my analysis is correct or if I have misunderstood it.
Let me add my analysis here. Take note that I have simplified a lot in order to fit them into a single page. For my case, the supply of the bridge are connected to VREF of the ADC and, R1=10k,R3 and R4 are 20k.
I also made assumption that the measured ADC value are summation of error free ADC result plus offset error (Eo in the picture). Maybe this is the part I was wrong?