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I'm designing a board where some external digital signals must enter a STM32 MCU GPIO input (VCC = 3.3V).

I would like to add simple ESD protection, a TVS diode, but I have a doubt about how to choose the Channel Operating Voltage. Should the Channel Operating Voltage be as close as possible to my GPIO voltage (in my case 3.3 V) or should it be higher, e.g. 5 V, 7 V or more?

I came across this catalog of TVS diodes, but I don't know if it is better to take for example an 824032813 which has a Channel Operating Voltage of exactly 3.3 V or if it is better to take for example an 824032815 which has a Channel Operating Voltage of 5 V.

I think it doesn't matter for my application, but I'm also interested in understanding from an educational point of view. Can anyone help me?

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2 Answers 2

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Should the Channel Operating Voltage be as close as possible to my GPIO voltage (in my case 3.3 V) or should it be higher, e.g. 5 V, 7 V or more?

Channel Operating Voltage is a non-standard term, at least in English, and I couldn't find any guideline or recommendation of its use from WE's application notes (I only did a quick search, I didn't dig deeper). Someone should write to their field application engineer to ask for a clarification.

But I believe that from the fact that there are 3.3 V and 5 V diodes, it's already a pretty clear indication that they're expected to be used at these logic levels. Thus, just select a 3.3 V part and you should be fine.

Still, if you want to be extremely cautious, select the next closest voltage level instead, which is 5 V. For example, the specification of the diode 824032813 has a Vch = +/- 3.3 V, Vbr = 4 V min. at 1 mA. So we know that, at 3.3 V, the current flowing across the diode is almost zero, but at 4 V, it's 1 mA. On the other hand, the worst-case logic voltage with a 10% error is 3.6 V. What happens between 3.3 V and 4 V? The datasheet is silent, even a "typical" curve is nonexistent. If Channel Operating Voltage is really meant to be the logic voltage that the diode is designed for, the leakage is unspecified but probably is still far away from 1 mA. But if it's just a synonym of Reverse Working Maximum Voltage, all bets are off, so a 5 V part is safer.

I think it doesn't matter for my application, but I'm also interested in understanding from an educational point of view. Can anyone help me?

Yes, you're right. For simple ESD protection on GPIO pins, TVS selection is trivial.

Consider the following factors when selecting an TVS diode:

  1. Reverse Working Maximum Voltage (VRWM)

    VRWM is the voltage where the TVS diode is guaranteed to stay off. This voltage should be slightly above the I/O logic level to ensure the diode is non-conducting. For example, for a 3.3 V signal, VRWM should be at least 3.6 V.

  2. Unidirectional vs. Bidirectional

    TVS diodes work by reverse breakdown. When an unidirectional TVS diode is forward biased, it's just a regular diode with a 0.7 V drop. Meanwhile a bidirectional diode clamps to its rated breakdown voltage at both directions.

    Bidirectional TVS diodes are safe for both AC coupled and DC coupled signals. But if the logic voltage is always positive, selecting an unidirectional diode is cheaper and provides marginally better protection for a negative ESD.

  3. Power Dissipation

    When designing with TVS diodes, the most difficult decision is calculating its energy-handling capability under a given surge energy and waveform. This is a non-issue for when you only need to protect ESD spikes, as they have negligible energy.

  4. Parasitic capacitance

    For high-speed I/O, a low parasitic capacitance is crucial. For example, 480 Mbps USB 2.0 should not have a parasitic capacitance higher than 5 pF. For these applications, you usually can find diodes specifically marketed for their protection. Meanwhile, for slow I/O, it's a non-issue.

    As a sanity check, the diode 824032813 has a capacitance of 350 pF, assume a conservative 50 Ω output impedance (logic output with source termination), this limits its 10%-90% rise time to:

    $$ 2.2 \text{ RC} = 2.2 \cdot 50\text{ }\Omega \cdot 350\text{ pF} = 38.5\text{ ns} $$

    Is it acceptable? Maybe, unless you're operating the GPIO line at several megahertz. In that case, you'd want a TVS diode with less capacitance.

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    \$\begingroup\$ Good summary. Maybe add a hint that a typical TVS will have a too high clamping voltage for most inputs, e.g. 8 V or more. An in-line resistor after the TVS limits the current accordingly. \$\endgroup\$
    – tobalt
    Jan 11, 2023 at 4:56
  • \$\begingroup\$ An in-line resistor of wich value? \$\endgroup\$ Jan 11, 2023 at 8:35
  • \$\begingroup\$ @FedericoMassimi Resistor is optional, one TVS diode is always better than no TVS diode! But a resistor can improve the effectiveness of ESD protection significantly. Resistance is a tradeoff, from a hundred ohms to a few kilohms, depending on how much voltage drop and signal slowdown are you willing to accept. Always include a resistor in the schematics and PCB layout, the value can be changed later or even deleted via a 0-ohm jumper link. \$\endgroup\$ Jan 11, 2023 at 17:58
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Should the Channel Operating Voltage be as close as possible to my GPIO voltage (in my case 3.3 V)

Yes absolutely. In other words, the stand-off voltage called VRM of the diode must be in line with the voltage of the GPIO.

As explained by 比尔盖子 at the VRM voltage, the leakage current of the diode is very low (nA range) BUT you have to know that all the reliability tests have been performed at this VRM voltage. What happens in terms of lifetime if you permanently bias the ESD diode at a voltage higher than the VRM? Nothing is guaranteed.

Selecting a VRM as close as possible to the max GPIO operating voltage should optimize the clamping voltage. The formula of the clamping voltage is VCL = VBR + Rd * IPP

  • VCL = clamping voltage.
  • VBR = Breakdown voltage. It is the voltage when the diode starts to enter in avalanche mode (generally VRM = 85% of min VBR).
  • RD = dynamic resistance. This is where the TVS makers technology & design skills make the difference.
  • IPP = peak pulse current. It is the current coming from the surge (ESD surge or any other transient surges)

You can see that lower the VBR, lower the VCL. In other words, lower the residual voltage at the GPIO pin.

To learn about ESD, you can watch this ST webinar : ST ESD webinar

And here is the link to the slides : ST webinar slides. From slide # 36, they show dedicated ESD protection for STM32. It may be of interest for you.

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