I know it is a very basic question but I couldn't really find an answer on the internet. Our lecturer told us it is used to reduce the number of transistors used in the design.
Our first case without an inverter at the end (AND gate):
This is the second design with an inverter (AND gate):
In the first design we used 4 gates, in the second it was 6, so how does this reduce the number of transistors used?
The four-FET ‘AND’ you show in your first diagram doesn’t provide proper gate bias for the FETs to switch correctly. It doesn’t really work.
More here: Why are the voltages the way they are in this transistor circuit?
The second diagram, a NAND followed by an inverter, is standard: n-FETs used in the pull-down network and p-FETs in the pull-up.
I think this question comes from a misunderstanding of how FETs actually work, a detail that a typical logic-FET diagram like yours (bubble on gate for p-FET, no bubble for n-FET) tends to obscure.
What's not shown in either diagram is the source substrate connection. FETs turn on based on their gate-to-substrate voltage.
In the second (working) diagram then, the substrates connected as follows:
Following this rule ensures that the gate-source (substrate) voltages applied to the FETs are driving them fully on or fully off. Then you get the switch-like behavior you expect: logic '1' turns on the n-FET, logic 0 turns on the p-FET.
The NAND gate implementation you show is not the one with the least number of transistors. It's possible to create a NAND gate with 2 nmos and 2pmos (see wikipedia).
We prefer this NAND gate over the four-transistor implementation of the AND gate because it helps prevent latch-ups. This question also lists some infos about why we want pmos in the pull-up and nmos in the pull-down network.
Inorder to get the non-inverted output i.e, if the inverter is not added at end of CMOS AND and CMOS OR gate u ca observe that the reverse or inverse output with respect to the truth table of OR and AND gate can be observed so the inverter is added.
