We have designed a PLL for an operating range of 11-14 GHz. The output of the VCO goes directly to the amplifier, and then to a divider, see the picture.

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Is there anything that affects PLL locking time or performance because we are placing an amplifier in it?

Can anyone please please clarify this?

  • \$\begingroup\$ Have you simulated it before asking this question. If so, what was problematic? If you haven't simulated it, then my advice is that you should. \$\endgroup\$
    – Andy aka
    Commented Jan 12, 2023 at 10:34
  • \$\begingroup\$ @Dinesh Is there a reason why you need an amplifier in the control loop? \$\endgroup\$
    – Don
    Commented Jan 12, 2023 at 17:59
  • \$\begingroup\$ Yes, Don. Output power of VCO is not enough power to drive the N-DIVIDER input for dividing.That is the reason we kept it amplifier in between. Is there any anything phase will affect? \$\endgroup\$
    – Dinesh
    Commented Jan 13, 2023 at 4:39

1 Answer 1


I'm not an PLL design expert, but you can get Amplitude noise to phase noise conversion.

If the amplifier is too noisy this can be translated into jitter, thus your output signal might not follow your input signal properly, and this noise can be translated to other blocks in your system. It'll be very jittery.

  • \$\begingroup\$ I really appreciate your response @ErnestoG. Which means you are saying placing amplifier in between VCO and N-Divider is not good option. Definitively, phase will affect right? \$\endgroup\$
    – Dinesh
    Commented Jan 13, 2023 at 9:09
  • \$\begingroup\$ @Dinesh I'm not saying is bad, but I'd suggest you do a system simulation assuming different noise values for your amplifier to check how jitter is affected. It could be that it doesn't matter because your oscillator phase noise is orders of magnitude more important, I don't know. Just saying you should take it into account before concluding is important or not. \$\endgroup\$
    – Designalog
    Commented Jan 13, 2023 at 9:48

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