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I have this schematic to digitally start and stop a power supply of a Raspberry Pi, and I want to be assured that the latch doesn't start by itself in the ON state when I apply power.

Of course, if it's ON and I cut the power and put it back again in short time, it will start ON again, because it is a memory cell. But this doesn't matter. I just want it to not start ON if I leave it OFF. Can I do something to make this happen ?

enter image description here

From the datasheet. The only way to force the output low is to have the Set low and Reset high, but I don't know how to achieve that.

enter image description here

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    \$\begingroup\$ The state is random at power up, unless you use the clear/set inputs to set state at powerup. \$\endgroup\$
    – Justme
    Jan 12, 2023 at 13:51
  • \$\begingroup\$ You are not using it as a D type latch realistically. You have it implemented as an SR flip-flop and ditto what @justme says. \$\endgroup\$
    – Andy aka
    Jan 12, 2023 at 13:52
  • \$\begingroup\$ It may be a system problem. For example, that might only work if the DC/DC converter is isolated. Otherwise you are just connecting circuit ground to RPi ground and unisolated DC/DC converter is grounded via RPi so all current bypasses the FET U6 and it can't control power to DC/DC converters. Which is why one of the first rules of thumb is never to switch grounds between devices (unless determined carefully how to do it if possible). \$\endgroup\$
    – Justme
    Jan 12, 2023 at 14:21
  • \$\begingroup\$ The DC-DC converter is isolated. It's PSD-15A-05 from Mean Well. But I haven't tried with the RPi connected yet, I just did some tests on this separate circuit, to see if it works well. And I don't declare that it works well until I can control the state in which it starts. \$\endgroup\$ Jan 12, 2023 at 14:27
  • \$\begingroup\$ You may put some extra capacitance or resistance on one side of the SR latch so it's guaranteed to start up slower on one side. \$\endgroup\$
    – user253751
    Jan 12, 2023 at 16:23

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To reset the CD4013B SRFF on power-up, your circuit needs to assert CLR while SET is negated.

Your existing circuit around CLR is shown below.

enter image description here

You can add the below circuit to your circuit. This will drive a logic HIGH pulse onto CLR for a short period after reset. The pulse duration must be longer than the supply rise time so the R101 and C101 component values would need to be set by yourself. Remember that R101 effectively has 101 kOhm in parallel with it (your R13 and R8), albeit through a diode. I recommend that your R101 and C101 values should ensure that Vc101 is below 3 V for at least 1 ms after the supply has stabilised. Make sure the tolerance of C101 is allowed for.

D2 effectively disconnects the high pulse circuit when C1 has charged and the voltage across R1 has dropped to 0 V. D1 discharges C1 when the power is removed and the rails fall.

schematic

simulate this circuit – Schematic created using CircuitLab

Note that the SRFF SET has priority over CLR so if SET is asserted during this time, the SRFF will be set. That may well be reasonable behaviour as if the input is active the circuit should respond to it.

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