5
\$\begingroup\$

I want to transform a type III analog PID into a discrete-time one so I can implement it on a PIC18F. The controller is for a buck converter.

When I apply the bilinear transformation to the analog transfer function

\$ s =\dfrac{2}{T}\cdot \dfrac{z-1}{z+1}\$

how much should T be when my switching frequency is 500 kHz and loop bandwidth is 60 kHz?

\$\endgroup\$
  • 1
    \$\begingroup\$ I'm not sure about a type III PID controller? I wasn't convinced that the internet was definitive about what "type III" means. Can you provide detail of the circuit you are trying to make digital. Include the switching regulator part please. \$\endgroup\$ – Andy aka Apr 9 '13 at 11:02
  • \$\begingroup\$ As pointed out in the answer below by CAGT: T is time between successive calculations in your filter loop. If all you are after is T then this answer is correct. If you want more details on designing your loop we need more information about the analogue controller you are trying to make digital. \$\endgroup\$ – Warren Hill Feb 3 '14 at 11:55
  • \$\begingroup\$ Are you sure about that loop bandwidth of 60kHz? That would mean your PID loop must run with at least 120kHz! \$\endgroup\$ – EvertW Apr 25 '14 at 11:57
  • \$\begingroup\$ Can you add some code and show how your schematics look? Probably many people are interested in microcontroller doing PID regulation. \$\endgroup\$ – Kamil Apr 26 '14 at 22:47
  • \$\begingroup\$ Here is a link that should help! biricha.com/converter/type/4 \$\endgroup\$ – user74867 May 5 '15 at 16:08
1
\$\begingroup\$

I think that the Type III Compensator you refer, is the one with 3 poles and 2 zeros (3p2z) used to stabilize a voltage mode buck converter. You do not describe the relationship between the loop execution frequency and switching freq. ("1 by 1" or "1 out of n"). I believe that Fbw = 60 kHz is very high to be handled with a PIC-18F - it would be more consistent with a DSP or DSC.

In order to be conservative:

  1. To avoid aliasing Fs > 2 Fbw. In practice: Sampling frequency should be 10 to 30 times the bandwidth freq.
  2. Another equivalent choice: T < 0.1 Tr, where Tr is the rise time of the open-loop system.
  3. The phase shift (degrees) in a given freq. F is -360FT. Since the ZOH (Zero Order Holder) contributes with a T/2 delay, the shift is -180F/Fs. Resulting in -180 deg. when F = Fs. So, for a stable design, pick a low T.
  4. In other hand, a very high Fs can lead to precision errors in a fixed point implementation: Remember that, with a very small T, the poles in z domain tend to unity, since $$z = e^{Ts}$$ resulting in very similar values, such as 0.999 and 0.99.
\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.