Low quiescent current, 50V high-side PMOS driver

Question

First, I never used Zener and BJT before, so if I made something stupid please explain, I'm eager to learn.

The project is battery-operated and has 8 to 16 outputs with an individually selectable voltage for each one ; the choice is either to directly feed the output from the battery (9S-12S so about a 27V to 50V range) or from the main 12V buck. These outputs will mainly be used as ON/OFF switches or at low freq (< 100Hz), driving up to 2A and consuming as less quiescent current as possible.

I tried to find an off-the-shelf high-side driver but due to the "high" voltage, chip shortage and support for 100% ON time (so no bootstrapping), the only few I found were really expensive (and I need up to 16).

So, after spending some time tinkering, I came up with this circuit. I tried to make it simple, but with 2 twists:

• a BJT (Q1) to quickly turn off the pmos instead of a resistor
• a "pulsed" current to quickly turn on the pmos, without violating the Vgs limit at any moment, before settling to a low quiescent current (~50uA)

^{simulate this circuit – Schematic created using CircuitLab}

The principle is quite simple, but will explained in 2 steps. The PMOS is a BUK6D120, but the NPNs are not yet selected (I will naively consider beta=100 for the discussion). First, considering only R4, Q2 and R1, this a low power static circuit:

• Q2 and R4 are used as a rough current sink that draws about 50uA ;
• R1 will have about 9-10V when traversed by 50uA, enough to have the PMOS fully on. However, this is not enough to correctly/quickly drive the PMOS.

Now, considering the whole circuit, when switching the input from low to high, C1 is seen as a short circuit and the current will be limited only by R4//R3~=R3 ; this will temporarily increase the current sunk by Q2.
C1 is selected so that the "pulsed" current last long enough for the PMOS to change state while not dissipating too much power in Q2. However this higher current will increase the voltage across R1 and must be clamped to a safe value by the D1 zener.
Once C1 is charged, the circuit goes back to a 50uA quiescent current.
Here the value are chosen to have a symmetrical 5mA source/sink to the MOS gate, which should allow it to fully switch in about 2us.
Finally, when off, only leakage current is consumed, and D3 allows C1 to discharge.

Basic simulations seem to show that it is working as intended, but I'm out of my comfort zone. Did I overlook something? Any tips or improvement ideas?

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Some notes:

• the circuit could be improved further by adding a push-pull stage before R2, but I feel it is not necessary in my case (should allow a few 100s mA and switching in a few 10s of ns). C1 could be lowered by an order of magnitude in that case.
• D3's anode could be attached directly to C1 for instant discharge, but feels unnecessary.

Answer 1

Yes, that looks fine.

Nice attention to detail as well, the diode to discharge C1 faster.

Some tweaks:

• D1 capacitance loads the voltage-gain node; since there's no current amplification in the pull-down direction (at the high side I mean), D1 can be placed at the output (Q1 emitter). This will improve risetime slightly (Q1 can pull it up instead of just the resistor).

• R2 is too small to do anything to rise/fall time: compare to the values of R1/h_FE or R3. Mind, it's still a good idea to have present -- to prevent M1 oscillation during commutation, especially with extra capacitance from G-S such as D1 (if moved as above). So, this is more of a note, really.

  Since the resistance is wholly noncritical, a ferrite bead could also be used.

To get faster switching and lower quiescent current, you could employ a complementary drive arrangement: a complementary emitter follower to the gate, then for level shifting, a differential signal pair, which can be current sinks from the low side for speed, or saturating switches for less current consumption. The high side receiver of that differential signal could be a couple of common-emitter stages, to invert and non-invert the signals back to a usable gate drive signal (which could in turn use a negative LDO to supply "-12V" referenced to VBAT). Such a circuit is typically used in CMOS level shifters; but as you might guess for an IC application, it takes a lot of transistors, so it's doubtful you'd want to employ it here.

A bootstrap gate driver would do, with BS tied to VBAT, and VS tied to "-12V" (again, relative to VBAT); but these draw surprisingly high quiescent current for battery purposes (ca. 0.3mA) so it's probably not an attractive solution. There may be edge-case issues like UVLO state, too: these are only ever used to drive NMOS, so the output may be default-low, the opposite of what you want for PMOS. (If they go open-circuit / tri-state when disabled, a pull-up resistor will cover this.)

There are also high-side load switches/drivers, which can include protection (over/under/reverse voltage, overcurrent, overtemp; current sense is also a common feature), but these may be on the expensive side, depending on what you're doing.

So what you have here is pretty good, as a cromulent, low parts count solution.