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Based on the JEDEC DDR3 documentation as shown below, when we are reading with burst length of 8 and starting column address of 010 (0x2), the burst order will be 2-3-0-1-6-7-4-5 for burst type of sequential. Why is that the burst order on this way, why is it not just simply 2-3-4-5-6-7-8-9? And why is that even we are on the starting column address of 2, the burst will still read column address 0 and 1 (since burst order is 2-3-0-1-6-7-4-5)?

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  • \$\begingroup\$ Note 1 mentions a burst length setting in mode register 0. Note that that spells two cycles of length four, both starting at offset 2: [(2, 3, 0, 1) (6, 7, 4, 5)]. Look how similar other offsets are handled. (Why digits 0-7 are decimal rather than hex, octal or base 11 escapes me.) \$\endgroup\$
    – greybeard
    Jan 14, 2023 at 12:30
  • \$\begingroup\$ Because that would be column 0x0, offset by two. But they are probably designed in blocks so that address 8 and 9 for example aren't available from the same transaction. The permutations allow shorter access times to words within a block. \$\endgroup\$ Jan 14, 2023 at 12:31

1 Answer 1

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CPU caches don't store individual bytes or words, they store "cache lines" which consist of a number of bytes, for example 64 bytes. When reading, the CPU always wants full cache lines, that's pretty much the "unit" of reads. So the memory will deliver the full cache line. Otherwise the CPU cache would require extra logic to know if each word in a cache line contains actual data.

Starting with the address that was requested is an optimization: the CPU is waiting on a read from that particular address, so it makes sense to deliver it first. The other reads are delivered to fill the cache line, also hoping the CPU will need them soon. If it's an array, the CPU will keep reading subsequent addresses, which by this point will have been read.

Due to the nature of DRAM, having to open pages etc, starting a burst takes a while but transferring more data is fast, so burst access by full cache lines makes sense.

Why is that the burst order on this way, why is it not just simply 2-3-4-5-6-7-8-9?

Reading word 9 would result in an incomplete cache line. It could also require the RAM chip to cross a page border and open a new page, which is very slow. It would interrupt the burst, which would defeat the point of doing a burst, and also require extra logic to handle that.

Basically, if you have several variables that are often accessed together, it will be faster to put them in the same cache line, so the address of the block should be chosen to do so.

However, if you have two variables that are owned by different CPUs, like locks, it pays handsomely to put them on different cache lines, because multi-core and multi-cpu concurrency usually has cache line granularity level. So if two locks are in the same cache line and two cores each want one of these locks, they will fight for ownership of that cache line.

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  • \$\begingroup\$ Thanks, it's clear now. One question, if I'm making a DDR3 controller then I have to consider that the starting address to know the order of the burst, right? But looking at the pattern of the burst for different starting column address I cannot see any kind of pattern, does that mean I have to hardcode all possible burst order? \$\endgroup\$
    – hontou_
    Jan 15, 2023 at 4:34
  • \$\begingroup\$ 0123 and 4567 are independently rotated so it's probably just incrementation and bit masking \$\endgroup\$
    – bobflux
    Jan 15, 2023 at 7:51

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