# How do high current paths work in PCB design?

Using a calculator like this one I see that the trace width required for 10 A is 9.36 mm at 2 oz (highest JLCPCB offers).

My IRLZ44N transistor has 2.54 mm spaced legs, so how does putting two 10 mm traces on them work? Needless to say I tried that but the router (let alone me) would never be able to solve it:

What are the options?

• Can you narrow the trace to fit the FET pin? Jan 14 at 23:10
• @Justme isn't it going to melt? Jan 14 at 23:12
• How many layers can you use? Jan 15 at 16:08

Looking closely at the calculator referred to, the trace width of 9.36 is for a trace on an internal layer and for a temperature rise of 10 degrees.

On an external layer the width is 3.60mm for the same temperature rise.

Allowing the temperature to rise by 30 degrees C, reduces the width to 1.85mm.

As suggested in the comments, necking down the trace to fit the pin is a viable solution. As shown in the calculator, the temperature will rise, but the attached wider portion of the trace and the pin of the FET will act as heatsinks. So the temperature rise will not be as severe as the calculator indicates. Further, employing tactics from the other answers will enhance trace reduction further.

The trace width is not based in when melting occurs but on a precise temperature rise. Carefully reading the calculator gives you choices to assist in your layout.

• I'm sorry if this is a stupid question, but are both layers external in case of a 2 layer PCB, Or am I supposed to solder conductors and those are considered external? Jan 15 at 11:28
• @php_nub_qq yes, the top and bottom layers both count as "external" in this case. The internal copper layers are between two (or more) layers of substrate; the substrate acts as an insulator between the copper and air, which is why internal layers' temperature will rise more sharply.
– Neo
Jan 15 at 13:50

According to your calculator, 9.36 mm is for 10C rise on an internal layer. Surface layers can be thinner since they're better cooled, so the obvious thing to do is to route on the surface layers. You can also choose to allow more than a 10C rise, especially if your trace will be short and/or connected to a large plane that can provide heatsinking.

For example, your calculator says that a 15C rise on a surface layer requires 2.8mm traces. Given your 2.54 mm spacing between source and drain, this should be pretty straightforward to route. You can probably do even better by routing on both sides of the board as well since you have a through hole part.

• So are both my layers, in the case of a 2 layer PCB, surface layers? Jan 15 at 11:32
• @php_nub_qq Yes a two layer board only has surface layers. A 4 layer board would have two surface and two internal layers. Jan 15 at 13:20

I understood your question in the way how to get it routed with this particular footprint, and not in the way how it "works" in general, so I did not care for trace width - tried just to get as much as possible.

The drain pin is a bit hard to get to on this component, though it is available on the case as well. If you want the component not laying flat on the board, and thus we can only use pin 2, I'd go somehow like this way:

This allows (ridiculous) trace width but of course can not be soldered by hand except with a very fat soldering iron.

Here the width of the traces to pin 2 would be (2.4 + 2.2)mm so 4.6 mm in total - that might be enough - and it can be as wide as you want outwards. I combined top and bottom layers (here each 7 mm wide traces on both top and bottom on each pin, to show there is no limit).

If you need a heat sink on the component mind that the case pin is on drain voltage!

The vias make it even harder to hand solder and might not be needed that near to the component, but somewhere you would need to stitch the two layers used for D and S.

Sometimes it is possible to put enough solder paste on the pads of such THT components to let the reflow process make the hard work for you. For this to work you might need some handdraw solder stop and solder paste openings - and of course an idea to hold the component during reflow, but it may be worth the effort.

It could be another interesting question to calculate how much solder paste area would be needed to get nice connections of such TO-packages by reflow soldering...

Here are some ideas.

1. Put the drain and source pins in 10 x 10 mm square fills.
2. Put a 10mm trace to the drain on top layer, and a 10mm trace to the source on the bottom layer (or vice-verse).
3. Put a 5mm trace to drain on both top and bottom layer, then put a 5mm trace to source on both top and bottom layer.

It is not actually required that the trace be 10 mm wide at every point. A short section that is as wide as practical can connect to the 10 mm wide trace.

There is no problem if you narrow the trace near the pin. However, this is not the best solution.

1 - You can use two traces (top and bottom) and halve the trace width.

2 - (The best one, in my opinion) Partially remove the solder mask over the trace; it can be all the way along the trace length or in some points, and add solder.

A rule of thumb is that doing 2, you double the trace capacity, so you halve its width.

This technique is very common in power supply PCBs.

• I'm pretty sure, though I can't recall a source, that adding solder on top of traces has been shown to have little to no impact on current capacity. It doesn't hurt, but it doesn't help either. Solder really isn't all that conductive, about 10% to 15% the conductivity of copper (solder joints are small enough that this doesn't usually matter), and the layers you get from wave soldering or putting normal thickness solder paste on it just aren't thick enough to do much. Jan 15 at 5:37
• @Hearth - but does it help with heat conductance/dissipation? Jan 15 at 14:11
• @davidbak Doubtful. Jan 15 at 15:14
• It's true that solder has 7x more resistance than copper. So a 0.5 mm thick layer of solder will halve the resistance of a 70µm/2oz trace. Typical reflow mask thickness is just 0.15 mm, but wave soldering can deposit more.
– jpa
Jan 15 at 19:49
• My reference is Mean Well. This technique is used in most of their power supply. I would like to share this video too youtube.com/watch?v=L9q5vwCESEQ Mar 28 at 15:00

Simply:

Trace width is calculated for long runs.

For short lengths, close in to pins, the current density can be much higher, but the power dissipation is less due to the short length; and the temp rise even lower still, because PCB copper is very conductive over length scales of a few cm.

In other words, current and heat spread out in the local area. Use a polygon/pour top and bottom for drain and source; this also keeps stray inductance low. Keep the length short: place the next components close nearby.

And, this is only concerned with temp rise; there are no higher-order or spooky effects (like electromigration), not at least until extremely high current densities. If it gets hot in operation, consider beefing it up next time, or adding some copper wire in parallel.

Incidentally, gate trace width can be almost nothing for temp rise purposes, but it should generally be a low-inductance path. A somewhat thicker trace may be desirable, as inductance is proportional to trace length and [roughly] inversely proportional to width. Depends what you're doing with it; inductance matters particularly for fast switching and high currents.