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When routing controlled-impedance differential signals (100 MHz) in the middle of a PCB, do the reference planes have to be directly adjacent? If no, is there any issue if there is another signal layer placed between the controlled-impedance layer and the reference layer?

Here is an example of one of my signals that is in question.

Below is the differential signal I have on layer "L3_MID2_H"

enter image description here

Below is the stack up of my PCB and as seen "L3_MID2_H" Top Ref is "Layer 1_MID2(GND)"

enter image description here

"Layer 1_MID2(GND)" is is shown below which appears to be OK.

enter image description here

However, the next layer "down" from "L3_MID2_H" is "L4_MID3_V" as shown below:

enter image description here

Then I have the bottom ref plane "L5_MID4 (PWR PLANE)" as shown below:

enter image description here

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  • \$\begingroup\$ do the reference planes have to be directly adjacent <-- yes but, the details may indicate alternatives. \$\endgroup\$
    – Andy aka
    Commented Jan 15, 2023 at 14:35
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    \$\begingroup\$ Could you show a diagram of what planes, traces, and adjacency you are thinking of? \$\endgroup\$ Commented Jan 15, 2023 at 14:56
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    \$\begingroup\$ If you're routing other signals between the reference plane then you don't have a controlled impedance traces. That might be ok or it might not, but if you want controlled impedance do not do that. \$\endgroup\$ Commented Jan 15, 2023 at 15:50
  • \$\begingroup\$ This really is not a whole lot different than routing controlled impedance single ended signals. The increased spacing between between the signal and a return plane is going to raise the impedance of that signal. Placing a conductor (signal) trace on a intervening layer is also going to impact ZO. How much depends on if the intervening trace is parallel or at right angles to the signal trace you care about and, if parallel, how long the parallelism is. My guess is that it would raise ZO, unless the intervening trace becomes a return path, \$\endgroup\$
    – SteveSh
    Commented Jan 15, 2023 at 15:53
  • \$\begingroup\$ This will abuse any copper that actually is adjacent as return conductor. If there are signals, then those signal traces will carry return currents of other signals.. It can lead to severe signal integrity issues. \$\endgroup\$
    – tobalt
    Commented Jan 16, 2023 at 16:38

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The differential nature of the lines is essentially irrelevant here; both traces in the pair are single-ended transmission lines whose return currents do not travel through the opposite line, but instead through a reference plane. This is in contrast to a twisted differential pair in a cable, in which the fields couple between the two lines and return currents are mutually shared.

There is a ground plane adjacent to L3_MID2_H, with a distance of 4mil, so the differential pair on that layer will be referenced to that plane. The fields will spread from the pair, through the dielectric, to the layer 2 ground plane.

The traces on layer 4, however, do not have an adjacent ground plane. They instead have an adjacent power plane. Referencing signals to a power plane is potentially problematic. If the power plane provides the lowest impedance return path for the currents, their flow will inherently generate a potential difference, which will manifest itself as power plane noise. If the power plane does not provide a low impedance return path, the fields will spread out further and couple to other signals, e.g. back through your differential pair on L3_MID2_H. This will lead to crosstalk.

This would be less of a problem if your stackup had a wider spacing between the two adjacent signal layers, because this would reduce the interlayer coupling between the two signal layers.

The impedance of the line will be affected in your stackup because there's coupling between the signal layers.

Ideally, every signal layer should have a ground plane next to it, and power traces should be run individually rather than using up an entire plane layer (unless you really need to shift a lot of current). You should also try to manage your stackup such that you have wider dielectric spaces between adjacent signal layers and smaller dielectric spaces between your signal layers and their reference planes.

For further learning on this matter, I highly recommend Rick Hartley's two talks - "The Extreme Importance of PC Board Stackup" and "What your differential pairs wished you knew".

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  • \$\begingroup\$ Not entirely irrelevant I would say; differential saves on current return path, so it's not a big deal if the plane(s) aren't well bypassed/via stitched to each other (but it doesn't hurt, and improves CM performance if it matters). Good note that DM coupling is less than normal mode coupling, i.e. the pair acts more like two independent traces; most of the value in diff pair routing is to keep CM currents low (reduces GND loop and supply noise), and to avoid DM-CM mode conversion (particularly when crossing other planes). \$\endgroup\$ Commented Jan 16, 2023 at 18:09
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    \$\begingroup\$ With wide (~board sized) pours/planes, I wouldn't be too concerned about the power plane noise comment; but considering MID4 shows a rather small outline in the area, this is also good to keep in mind. Good answer. \$\endgroup\$ Commented Jan 16, 2023 at 18:11
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    \$\begingroup\$ Half way through this answer, I thought: "This be Rick Hartley speech". And when I saw the references at the end I knew why :) +1 \$\endgroup\$
    – tobalt
    Commented Jan 16, 2023 at 19:19
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Try to stagger traces that occupy the same space between planes -- so, those on MID2 and MID3. Avoid parallel routes that will couple into each other. It looks like the purple traces could be moved up, so the diagonal-up-right segments clear the green traces. Likewise the green traces can be moved down and right.

Assuming this doesn't increase propagation delays past limits, of course.

I would avoid pouring ground on signal layers (like MID2), unless you have particular reason to do so. Some clearance beside the diff pair is probably a good idea (10-15 mils?). If you must, stitch it well, lest the slot created in it by the trace(s) become a resonator that affects not only signal quality of the trace(s)/pair but couples to nearby (i.e. MID3) traces as well.

Reasons for such pouring might include absolutely having to have more wide connections (probably power, local supplies), or GND for better shielding between adjacent pairs (high priority signal quality / low jitter?). The stitching vias will cost more layout area (depending on how many layer pairs you have; I do see blind/buried vias are already in the design).

Don't worry about impedance comments. Simply use whatever trace width and pair spacing is calculated for the spacing between planes, and desired impedance (DM, and CM if possible / needed). This is an asymmetrical stripline arrangement.

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