I am interested in transmitting both digital data and power over a single coaxial cable between two FPGAs. Communication should be at least half-duplex. Communication speed should be on the order of 50-100 Mbps (something like ECL might be required?). Power is coupled in via an inductor biasing network in the same way as some "power over coax" GMSL SERDES pairs use. Here is a block diagram:
I'm looking for suggestions on how to fill in the black boxes, which take bi-directional IO to/from each FPGA and translate it into something capable of driving and receiving from a 50-ohm terminated (both end) coax that is biased with a voltage rail (power over coax; 12V in block diagram is an example anywhere from 5-12V is fine). I would like to use a minimum of parts. Data serialization, error detection, DC balancing, etc can take place inside the FPGA using e.g. PonyLink or something similar. I'm looking for the simplest and smallest translation scheme.
Why do I want to use a single coax? Because the circuit on the Vout side of the block diagram will be carried on a mouse's head for neural recording purposes. Any additional cabling is a mechanical hinderance to the animal. We are currently using a DS90UB95x SERDES pair and a 0.33mm OD microcoax which works well, but is power hungry. We want to reduce power consumption and size because we do not need the large data rates afforded by GMSL devices, which are meant for cameras typically.
Thanks.
