Pulse transformer for two switch flyback converter

Question

I would like to design a pulse transformer for a two-switch flyback converter, with a 1:1:1 turn ratio (1 input 2 outputs). I have troubles choosing the correct Volt-second and inductance.

My MOSFETs have a gate capacitance of 25nC each and I would like a rise time of 100 ns. This lead to a peak current to charge the gates of I = 2*Q/dt = 0.5 A. The minimum switching frequency is about 40 kHz, so ton(max) = 25us. The gate voltage (from PWM controller) is about 15 V. The duty cycle is 0.45 maximum. Does it mean that I need a pulse transformer with a Volt second of 15 * 25 * 0.45 = 168.75 us minimum? What about the inductance value? How do I choose ferrite core and turns if I want to wind it myself? Thank you.

Answer 1

FYI, current and charge aren't too important; we will convert this into a network, i.e. a circuit having some bandwidth and impedance, and the current will simply follow from that.

25nC at 15V is \$C = \frac{Q}{V}\$ or 1.67nF average/equivalent capacitance (assuming this is measured at 15V; Q_G is usually measured at 10V, so this figure should be extrapolated from the given value or the gate charge curve). Since you're driving two in parallel, they look in parallel on the primary side, which may be relevant in the transformer design, or can be worked around.

100ns rise into 1.67nF is the 10-90% time, or 29.5% of a sine cycle, or 3MHz bandwidth needed. 1.67nF at 3MHz is 32Ω impedance, and \$Z = \sqrt{\frac{L}{C}}\$ requires L < 1.7µH. This is the maximum leakage inductance from primary to each secondary; we can make up the difference with resistance, or enjoy the extra speed (assuming the load circuit can handle it). Note that we need to make up at least R = Z to get reasonable damping; less resistance would give too much ringing.

We can ignore magnetizing inductance during the switching transient, so the equivalent circuit is a series R-L-C network between driver (some resistance), transformer (leakage), and gate (capacitance). Preferably additional resistance is in series with the gate, since that encourages current sharing, as opposed to on the primary side at the driver.

As for magnetizing inductance: as large as possible. Generally an ungapped μ_r > 2000 ferrite core will do well enough, which encompasses basically any medium frequency power ferrite (e.g. 3C90 and equivalents); and 5-10k are available. Also wide and short (i.e. high A_e and low l_e for the size) core shapes maximize inductance: P, PQ, RM, EQ, ELP and others are good choices.

Flux: 45% is close enough to 50% we can use the (full wave) square wave form: $$N = \dfrac{V_\textrm{pk}}{4 F B_\textrm{max} A_e}$$ The \$V_\textrm{pk} / (4 F)\$ part is peak flux, if we're shopping for off-the-shelf types.

We will need AC coupling on the primary, and DC restore networks on the gates. The applied voltage will be 15V peak-to-peak, so use 7.5V peak in the above equation. We will also need damping on the coupling capacitor(s) so that, when PWM changes suddenly, the shift in DC/baseline does not cause overshoot or saturation. We should choose saturation double or so to help with this.

So your calculation is correct, while this also explains that technically less (half) is needed under steady-state, but also more may be beneficial (due to sudden changes, or startup).

^{simulate this circuit – Schematic created using CircuitLab}

So we get a circuit something like this, values just for illustration, and drawn with two transformers as there's no multiwinding symbol in the library here.

The switching transient equivalent includes L2-R7-C6, and the rest can be ignored (as the L1 and C5 are much larger). Again, L2 is unavoidably a part of the transformer (leakage, LL) so we can't ignore it, but we can minimize it, or design for a particular value.

The DC/baseline equivalent includes (C5 || (C7 + R8)) + L1. We again choose R8 = Z, or \$\sqrt{\frac{L_1}{C_5}}\$. C7 then must be larger than C5 (at least 3 times) so that R8 acts as a dominant loss on C5. This saves us from using ESR for damping, which would interfere with the lower impedance switching path.

Transformer design

The easiest way to design for leakage is to apply transmission line transformer principles. We make a 1:1 primary-secondary pair from transmission line (e.g. twisted pair), and in this case since we need two secondaries, we can twist four together (taking opposing pairs for primary in parallel, the others for secondary), or use separate pairs, whatever is fine. The impedance of such a line is about 100Ω, so the inductance is \$\mu_0 \frac{z_0}{Z_0}\$, for \$z_0\$ transmission line impedance and \$Z_0\$ the impedance of free space (~377Ω). So in the ballpark of 0.3µH/m. The more wire length is used, the higher the leakage inductance.

If we need too much wire length (turns and mean length per turn) to meet the required flux, we need to choose a lower impedance TL, such as star quad per pri-sec pair, or multiple pairs or quads in parallel.

Wire size can be quite small, because RMS current is quite small, probably dominated by magnetizing current. Especially if many parallel pairs are required, you'll probably have a hard time finding wire small enough -- while still meeting isolation requirements -- to run into ampacity/loss issues. So don't worry about it, focus on signal response

Since LL doesn't need to be very small here, probably two pairs will suffice. And functional insulation (if this is primary side control?), so plain enameled wire will do.