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For reference, I am talking about a conventional push-pull converter topology as discussed e.g. in this question.

Wikipedia has the following to say about transistor timing in the push-pull converter (emphasis mine):

If both transistors are in their on state, a short circuit results. On the other hand, if both transistors are in their off state, high voltage peaks appear due to back EMF.

  1. Why is this so? Don't the secondary diodes present an easy way out for the flyback energy? I suppose the voltage on the inductor terminals will rise only to the output voltage + diode drop before it can result in a relieving current flow on the output side. (I had some issues with oscillations in simulating this converter, so I cannot easily tell from the simulations.)

There is also the following sentence in wiki:

If the driver for the transistors is powerful and fast enough, the back EMF has no time to charge the capacity of the windings and of the body-diode of the MOSFETs to high voltage

  1. I don't understand this at all. Is that about the FET output capacitance working as a snubber for a short time? How would that be related to the gate driver?
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    \$\begingroup\$ Leakage inductance will always cause a primary side back-emf. \$\endgroup\$
    – Andy aka
    Jan 17, 2023 at 15:59

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Possibly the term "back-emf" is confusing, since "electro-motive force" is a term used in motors and generally not in inverters. However, engineers sometimes uses it to convey the idea of energy stored in an inductor. No transformer has perfect mutual inductance; there is always some self-inductance or "leakage inductance" on the primary when transformers are theoretically modeled, as Andy aka points out. In the model, this inductor is not coupled to the secondary and acts as an independent inductor. Since there is a current flowing in the primary, the voltage on the inductor is L*di/dt. When you turn off both MOSFETs, di/dt is very large and so the spike occurs, with voltage sometimes rising to the avalanche voltage of the MOSFET.

In answer to your second question, I believe the author is saying that if you can time the switching so that if transistor turns "on" at close to the same time that the other is turned off, the energy loss from switching spike is diminished. Perhaps the author was trying to use plain English to describe the switching. It should probably be edited to remove the reference to back-emf.

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