I have been trying to decide the best single-supply non-inverting op-amp topology to use the ADC of an ATmega uC for capturing the signal coming from SCT013-030-0-30A-0-1V split-core current transformers.

The rated output of the sensor is 1 V, so the signal to be captured is a 50 Hz sine with a max. peak-to-peak amplitude of \$\small2\times\sqrt{2}=2.8284~\mathrm{V}\$.

Assuming that the A/D needs inputs in the 0-5 V range, I want to offset the signal by +2.5 V, in order to get a 50 Hz sine with a peak-to-peak range of 1.0858 to 3.9142 V. Furthermore, I'd like to amplify the signal by \$\frac{2.35~\mathrm{V}}{\sqrt{2}~\mathrm{V}}=\small1.6617\$, to better use the range of the A/D (0.15 V to 4.85 V).

I used the generalisation of a summing amplifier as a reference, and I focused on gain 1 at first.

Summing amplifier

In my use case, there are two positive inputs only,

  • \$v_{p1} = v_i\$
  • \$v_{p2} = v_{cc} = 5~\mathrm{V}\$

I can achieve \$v_o = v_i + \frac{V_{cc}}{2}\$ with or without \$R_{cp}\$:

Option FA:

enter image description here

Option FB:

enter image description here

I am unsure about which one is better. On the one hand, the gain in FA is 1.5 and the gain in FB is 2. Hence, I'd intuitively take the smaller gain, since noise is amplified along with the signal. However, in FA, the current flowing through \$R_{p2}\$ needs to flow through \$R_{p1}\$, and through the sensor. I wonder if that can somehow change the behaviour. Conversely, in FB, the current flowing through \$R_{p2}\$ can flow through \$R_{cp}\$.

As an alternative to adding the signals through the op-amp, I also considered using a divider as the reference of the sensor, instead of having it connected to ground:

Option FC:

enter image description here

Such a setup allows using the divider for multiple op-amps (each buffering one sensor). Yet, I wonder if this topology has some drawback, such making it less straightforward to match the impedances.

Transitient simulation of FA, FB and FC achieves the same result.

Then, I considered the case with gain 1. Option GA is the same as FA, with adjusted resistor values to achieve \$v_o = 1.667 \times v_i + 0.5 \times v_{cc}\$:

enter image description here

The same question as with FA and FB arises: is it desirable to add a resistor from V+ to ground and adjust the impedances?

Option GB:

enter image description here

Moreover, when adding the offset through a divider, \$R_{cn}\$ can be connected either to ground or to the reference of the sensor:

Option GC1:

enter image description here

Option GC2:

enter image description here

In option GC1, the bias is amplified by the op-amp. Therefore, the divider needs to be adjusted proportionally. Conversely, in option GC2 the op-amp is amplifying the signal only.

Transitient simulation of GA, GC1 and GC2 achieves very similar results.

Overall, I'd be grateful to receive any guidance that helps me pick GA, GB, GC1 or GC2.

As additional context:

  • GA and GB allow to easily create a low-pass filter by adding a capacitor between V+ and ground. GC1 and GC2 would require adding a resistor between the sensor and V+ as well.
  • The design is expected to include 5 sensors. Hence, reusing the reference divider (GC1 or GC2) might reduce the number of components on the board.
    • It might be sensible to buffer the divider, in order to decouple the reference from the amplifiers.
  • \$\begingroup\$ Just bias the CT outputs at 2.5 volts. If necessary, use an op-amp to buffer the 2.5 volts. No need to speculate on anything else. \$\endgroup\$
    – Andy aka
    Jan 18 at 21:16

1 Answer 1


Perhaps you can avoid using the op-amp entirely, since the CT is a (relatively) low impedance source:


simulate this circuit – Schematic created using CircuitLab

You could combine the bias resistors between channels, however that would cause a certain amount of cross-talk, and buffering it adequately may be more trouble than it's worth.

This assumes the MCU is okay with a 5.7K source impedance, and provides a LPF with a cutoff frequency of 1/2pi5.7kΩ*100nF ~= 280Hz.

Whilst you're losing a bit of ADC range, you've got the advantage of a bit of overrange capability. There will tend to be some DC component in the resulting ADC readings (after the nominal bias reading is subtracted) however you could take a long-term average of each input and subtract that rather than using half the full-scale rating, since the CT will have average 0V output.

R4 also provides some protection against spikes from input current surges, which could easily exceed the supply rails. You can add diodes (eg. BAV99 for each input) for more protection if you like. If you're getting continous spikes that exceed the rails by more than a couple hundred mV it may cause cross-talk.

  • \$\begingroup\$ Thanks for taking your time on this question! As far as I understand, your proposal is equivalent to option FC, but it places a LPF (R2 and C2) instead of a buffer (op-amp). As you mentioned, R4 also provides some protection. Would it be feasible to introduce scaling (1.66) in such resistor based solution? Or do you suggest it's better to use ~60% of the ADC range rather can trying to amplify the signal? \$\endgroup\$ Jan 18 at 21:59
  • \$\begingroup\$ I think it's better to avoid the amplification. You could consider a lower (and regulated) precision Vref for the ADC if the chip supports it. Then you'd divide off Vref. \$\endgroup\$ Jan 18 at 22:06

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