Moving comments to answer, with more detail.
NRST is an "active low" signal, meaning when low (as you have it, tied to ground) will put the chip in reset and keep it there. The processor can’t run when in reset and this completely explains the DEV_TARGET_HELD_UNDER_RESET error.
The chip has an internal pullup (Rpu, nominally about 40k) that will pull NRST high and out of reset.
The recommended circuit shows a capacitor and a momentary contact switch.
The small capacitor to ground is a good idea for two reasons:
- Upon power up the capacitor will charge via the Rpu resistor. The charge time is approximately .1u * 40k = 4ms. This ensures a valid reset pulse at power on. Without it there is essentially no reset pulse being supplied so the processor may not boot properly (although there may be some other internal reset mechanism to handle the power on case).
- As Figure 22 note 1 says, this capacitor also protects against “parasitic resets”. If pin is floating (no cap) then NRST is a fairly high impedance (40k) node that could be susceptible to high frequency edges on nearby traces capacitively coupling to NRST and causing bogus resets.
The pushbutton is optional, providing a manual way to temporarily discharge the capacitor and reset the device. When you let go the capacitor will charge again to VDD via Rpu.