I have a custom embedded board with an MPU (i.MX6ULL) interfaced to a DDR3L. After noticing occasional hangs and crashes, I started tinkering with the DDR Drive Strength settings and was surprised how sensitive the board is to these - out of a range of 7 possible Drive Strength settings, only 1 setting works perfectly and only 1 other setting works moderately well (still hangs/crashes at first boot after power-on, but then works fine after a reset).

I can't seem to make sense of why the particular setting which works well does work well. The Drive Strength setting (IMX6ULLRM doc) ranges from 240 Ω to 34 Ω (240 divided by between 1 and 7) and the setting which works perfectly is 48 Ω. The calculated impedance of the traces however is 60-70 Ω (96 Ω on the diff pairs, 57 Ω for the individual diff pair tracks), but testing with a Drive Strength setting of 60 Ω does not work at all - actually the other setting which works moderately well is 40 Ω (even lower).

(Trace impedances have been calculated using the Saturn PCB Toolkit using the PCB manufacturer board specs and the relevant trace widths and spacings.)

  • What is going on here?
  • Is there a way to calculate drive strength based on trace impedance, or is it just a case of trial-and-error testing to find one which seems to work?
  • Also, why does the 40 Ω setting fail at first boot after power-on, but then work fine after the board has been powered for a while?

Some more technical info/specs:

Layer Stackup (according to PCB manufacturer website - I am trying to confirm this with them however they are on holiday at the moment):

Layer Stackup


Schematic 1

Schematic 2



Traces (top and bottom layers) are 4th, except for differential pairs which are 5th (with 5th spacing). Inner layers are 1.35 V (inner 1) and GND (inner 2) planes. I didn't pay a huge amount of attention to impedance calculations when doing the PCB design, as I'd read an article online indicating that tolerances with these "relatively slow" high-speed designs were not that critical.

  • 1
    \$\begingroup\$ The rise and fall time of silicon MOSFETs varies with temperature; specifically they slow down as they heat up. Your board very likely has significant reflections at lower temperature (a common problem). \$\endgroup\$ Commented Jan 20, 2023 at 12:07
  • 1
    \$\begingroup\$ Read this Micron technical note. \$\endgroup\$
    – CL.
    Commented Jan 20, 2023 at 12:28
  • \$\begingroup\$ @PeterSmith Thanks will be interesting to do some tests at different temperatures. I'll put a board in the fridge / heat a board up and try again. The setting which works "moderately well" will reliably hang each time after power-on however, even if this is done only a few seconds after removing power. \$\endgroup\$
    – Dane
    Commented Jan 20, 2023 at 14:48
  • \$\begingroup\$ @CL. Thanks that looks very helpful! Skimming through I see that DDR3 only supports 34Ω and 40Ω drive strengths, sometimes 48Ω. Interesting that the only setting which seems to work in my case is 48Ω. \$\endgroup\$
    – Dane
    Commented Jan 20, 2023 at 14:48
  • \$\begingroup\$ If you selected the controlled impedance option when ordering the PCBs, then request an impedance measurements report from the fab to confirm the exact impedances in your case. Calculators are not accurate. \$\endgroup\$
    – Abdella
    Commented Jan 21, 2023 at 8:43

1 Answer 1


With drive strength changes, you are trading off rise/fall time (slew rate) for undershoot, overshoot, or ringing.

Given a fixed trace impedance, as you decrease the drive strength (by increasing the source impedance in this case), you reduce the edge transition speed and also reduce or undershoot, overshoot, or ringing.

It is usually considered good design practice to have a slightly under-damped interface, so that you get the minimum transition time with a bit of undershoot or overshoot on the transition, but no ringing. This may be why your design works best with the 48 Ω driver and your 60-70 Ω trace impedance.

Did you model/simulate this?

  • \$\begingroup\$ I'm relatively new to high-speed design and don't currently have the tools to simulate this - can you provide recommendations? \$\endgroup\$
    – Dane
    Commented Jan 20, 2023 at 14:54
  • \$\begingroup\$ Probably not something that's cost effective. In my day job, we use SI tools that are part of a massive, expensive EDA suite, like Hyperlynx (from Mentor Graphics) or Spectre (from Cadence). \$\endgroup\$
    – SteveSh
    Commented Jan 20, 2023 at 15:36

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