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Title pretty much says it all: Should arrays of thermal vias be square or hexagonal?

The closest packing of a circular array with constrained distances would be on a hexagonal grid. For a given unit distance \$d\$ between points, the required area per point is \$d^2\sqrt{3}/2 \approx 0.866d^2\$. (See for example https://en.wikipedia.org/wiki/Hexagon#Parameters where the distance between center and edge is \$r=d/2\$, half the distance between hex cell centers.) Square grid arrays with distance \$d\$ between points require an area of \$d^2\$ per point. So hexagonal arrays can pack in about 15.5% more thermal vias per unit area than a square array having the same minimum distance between vias. (Which should provide lower thermal resistance and higher thermal capacity.)

Aside from the fact that square arrays are simpler to create, is there any other reason to prefer a square array of thermal vias over a hexagonal array?

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    \$\begingroup\$ I use square/rectangular arrays for general purpose things, because they are slightly easier to make. And I do use hex arrays when I want to squeeze in as many vias as possible, e.g. for cooling. For very small pads under components, I anyway often end up with a situation where 4 vias on a rectangle are the most I can fit in that rectangular pad - with the next best thing being 5 in a 5-on-dice kind of pattern. \$\endgroup\$
    – tobalt
    Jan 20, 2023 at 19:00
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    \$\begingroup\$ A quincunx: en.wikipedia.org/wiki/Quincunx \$\endgroup\$
    – vir
    Jan 20, 2023 at 20:43
  • \$\begingroup\$ there's a word I haven't heard in a long time!!! en.wikipedia.org/wiki/Galton_board \$\endgroup\$
    – Jason S
    Jan 20, 2023 at 22:17

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If they are just for thermals, I am fully with you that they are better as hexagonal arrays. However, if you need current to flow sideways through the plane, you might find the extra loss of copper plane is detrimental.

This is not a problem directly under MOS pads though, since they have substantial lumps of copper to conduct sideways.

I am now changing some of my designs to take advantage of this.

Bear in mind also you can have copper filled vias for more money.

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  • \$\begingroup\$ "However, if you need current to flow sideways through the plane, you might find the extra loss of copper plane is detrimental." -- sounds like a good topic for a technical paper! \$\endgroup\$
    – Jason S
    Jan 20, 2023 at 19:10
  • \$\begingroup\$ "Not a problem directly under MOS pads" -- indeed, unless you're heatsinking directly opposite (back side high-K thermal pad?), only the perimeter is doing much work. The vias can even be slightly outside the pad outline, where they can be tented to avoid wicking solder (when paste-reflow soldering); the slight lateral distance through top copper has little effect. \$\endgroup\$ Jan 20, 2023 at 20:03
  • \$\begingroup\$ Conversely, if wave soldering (or enough excess paste / paste-in-hole can be added), solder-filled vias, in pad, can reduce their Rth by maybe 20-50% (depending on hole i.d. and Cu plating). Again, little advantage for convection cooling, but may be helpful for conduction. Downside: the solder tends to bulge out where it fills holes / pads, so a thicker thermal pad is likely required. \$\endgroup\$ Jan 20, 2023 at 20:05

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