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I'm trying to get a PIC18F46K40 I2C interface to work with a M24M01-D EEPROM, however I'm having problems where my code is checking for the I2C bus to be idle before initating a start condition using the following (which seems to be fairly common when looking online):

while((SSP1STAT & 0x04) || (SSP1CON2 & 0x1F));

The first time a I2C start condition is set (by setting SEN high) it uses this check to ensure SEN (and other things) are in the right state and the code then sets SEN high. This works fine, however, when doing subsequent reads/writes on the bus that re-uses this code to check the bus is ready SEN is still stuck at "1" and therefore the while loop never exits.

It's my understanding that after setting SEN high the hardware should pull this low when the bus is idle, therefore I'm starting to think this could be a hardware fault but I'm really not sure what this means.

I do also have a I2C temperature sensor on the same bus which seems to be fine for what that's worth, although it's using I2C code generated by MCC, whereas this EEPROM code is taken from:

...with some modifications.

The SDA and SCL lines are pulled up to 5 V via 4.7 kΩ resistors.

Putting a DMM on the SDA and SCL lines show them both high while it's waiting for the bus to be idle; I'm not sure if this is right. I don't have a scope to hand to see any more detail.

Any advice? This is running on a newly manufactured test PCB designed specifically for testing this, so there's very little on it, but it is a newly designed/manufactured assembly. I feel like I'm going round in circles trying to work out if this is a H/W or S/W thing.

The XC8 code is here if anyone is interested.

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    \$\begingroup\$ Would you please share a bit more of the code? At least the I2C setup part should be here. Is there anything else on the same I2C? If so, does the other component work? \$\endgroup\$
    – datenheim
    Jan 30, 2023 at 16:35
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    \$\begingroup\$ SDA and SCL should both be high when the Bus is idle. Do you finish the first transaction with a NACK? The NACK will tell the slave to reset the internal state machine. \$\endgroup\$
    – T Andersen
    Feb 2, 2023 at 9:23

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