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I've been working on some timing diagrams and I keep mixing up the behaviors for the different flip flops.


EDIT:

I think I have the logic correct. If someone could please let me know if I'm anywhere close, I'd greatly appreciate it! Here's what I believe is how Y2, Y3, and Y4 should behave.

If anyone can let me know if I'm close, it'd make my day! Thanks.

Black is what was given and red is what I've done so far.

My predicted solution

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  • \$\begingroup\$ This looks a lot like a homework exercise. You should really try to show what you've done so far. The way you put it out there it looks like "gimee the answer". \$\endgroup\$ Apr 10 '13 at 2:08
  • \$\begingroup\$ I've been working on it. Each time I trace it and keep track of the values, I get a different answer. I don't understand how to determine when the values change, where they change, and why. I seriously have gotten 7 or 8 different solutions. I'll update it in a moment, sorry. \$\endgroup\$
    – Justin
    Apr 10 '13 at 2:15
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    \$\begingroup\$ This problem looks like it's testing if you know how various flip-flops work. Essentially, for clocked flip flops, the output of the flip flop will only change on a rising or falling clock edge, so you only ever care about the clock edges. Which edge you care about, and what the input is in relation to the output, is based on the flip flop type and is what they're testing here. \$\endgroup\$
    – stanri
    Apr 10 '13 at 2:39
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    \$\begingroup\$ No. The edges of X (the T input for Y1) do not matter. The T input is not edge-triggered, only the clock. The level of the T input matters at the time that the clock is jumping from 0 to 1. The clock tells the flip-flop when to sample the T input. When it's not being sampled, the input doesn't matter. \$\endgroup\$
    – Kaz
    Apr 10 '13 at 4:51
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    \$\begingroup\$ If both T and the clock change state at the same time, that is a bad thing: it is a setup/hold time violation. Your homework problem carefully avoids this. Note how X and CLOCK never change at the same time. \$\endgroup\$
    – Kaz
    Apr 10 '13 at 4:52
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It looks like you are almost there, except that you are mixing up the behavior of the T input and the clock.

The way you have solved for the T flip flop looks like you believe that the high values of the clock specify "toggle requested" and the rising edge of the T input actually triggers the toggle.

But in fact it is exactly the other way around! A high value of the T input specifies a request to the flip-flop that "a toggle is requested", and the rising edge of the clock is the trigger. If T is high, while a clock edge arrives, then the flip-flop toggles. If T is low while the edge arrives, nothing happens.

It looks like you understand the concept, but you mixed up the roles of the signals.

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  • \$\begingroup\$ so instead of basing the time of Y1 on X, I should use clk? Like do what I did already, but use clk? \$\endgroup\$
    – Justin
    Apr 10 '13 at 4:10
  • \$\begingroup\$ Yes, base the time on the clk! \$\endgroup\$
    – Kaz
    Apr 10 '13 at 4:11
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    \$\begingroup\$ In other words, suppose you had given signals in which the T input rises at exactly the same time as the clock. That situation is indeterminate! The T signal has violated the constraint on setup time, so there is no guarantee that it will be properly registered. Your homework problem carefully avoids asking you this! The X signal is carefully skewed so that the changes do not coincide with clock edges. \$\endgroup\$
    – Kaz
    Apr 10 '13 at 4:34
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    \$\begingroup\$ Y2 has a level-triggered clock input, so basically it acts like a valve. When the clock is high, the D flip-flop follows what the input is doing, but when the clock is low, the flip flop ignores the input. About Y3, you are wrong because the flip flop does not toggle since it is a D flip flop, not a T flip flop! On the clock edge, it simply accepts the input and stores it. Y4 is triggered on the negative edge and its a JK flip flop: you should study those in detail. \$\endgroup\$
    – Kaz
    Apr 10 '13 at 6:31
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    \$\begingroup\$ See here: en.wikipedia.org/wiki/Flip-flop_%28electronics%29#JK_flip-flop When you tie the inputs of the JK flip flop together, you basically get a toggling flip flop like a T. But of course, this one is negative edge triggered so you cannot just copy the diagram from Y1. \$\endgroup\$
    – Kaz
    Apr 10 '13 at 6:33

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