I am designing a direct-coupled two-stage amplifier with the following design constraints.

  • VCE swings of both BJTs should be the same
  • 2nd stage current (IC2) should be between 10 or 20 times the 1st stage current.

This is the schematic with the relevant symbols:


simulate this circuit – Schematic created using CircuitLab

The specifications of the amplifier are as follows:

Parameter Value
Vpp (output) 5 V
Gain 500
Supply Voltage 15 V
Load 1 kΩ

I have followed the following design procedure:

  1. Derive the small signal model. I choose R5 to be 100 Ω. Using the small signal model and the gain equation which is A = R5 · hFE/R3 I obtained R3 to be 39 Ω (giving me a gain of 564 theoretically). Small signal model used

  2. Choosing VCE of both stages to be 6 V to avoid signal clipping

  3. Considering the AC load lines slope (~1/90 Ω), I set ICQ2 to be ~41 mA with R4 = 120 Ω. Now my VB2 is at 9.3 V.

  4. Staying within the constraints for the second stage current, I choose R1 = 1.6 kΩ and R2 = 1 kΩ.

  5. Then, on the biasing side of the input stage, by calculating VB1, I set Ra = 3.9 kΩ and Rb = 1.8 kΩ.

  6. I randomly choose all the capacitors to be 1 μF.

Values used from the datasheets of the BJTs are:

Parameter Value
hFE (Q1 and Q2) 220
hFE (Q1 and Q2) 120
VBE (Q1) 0.66 V
VBE (Q2) 0.7 V

To summarize the values I have chosen:

Element Value
R5 100 Ω
R3 39 Ω
R4 120 Ω
R1 1.6 kΩ
R2 1 kΩ
Ra 3.9 kΩ
Rb 1.8 kΩ
Caps 2.2 μF

When I simulate this setup in Multisim I don't get the expected output; I get a maximum gain of ~250.

AC Sweep of Simulation

(Q1) Why doesn't the calculated gain match the simulated gain?

(Q2) When this amplifier was physically implemented an even lower gain was obsereved. A decent gain close to the required amount was achieved only when R3 was set to 4.7 Ω, but that too quickly settles at a gain of 150 after a while. What causes this? Is it temperature effects or something else?


2 Answers 2


From what I see Ic1 is around 4mA and Ic2 around 45mA.

Thus, \$r_{e1} = \frac{26mV}{4mA} = 6.5\Omega\$ and \$r_{e2} = \frac{26mV}{45mA} = 0.58\Omega\$

So the voltage gain of the first stage is around

$$A_{V1} = \frac{R_1||( h_{fe2}*r_{e2})}{r_{e1} + R_3||R2} \approx 2.5[V/V]$$

And the second stage gain will be around

$$A_{V2} = \frac{R_5||R_L}{r_{e2}} \approx 155 [V/V]$$

Therefore the overall gain will be around 2.5*155 = 380V/V for Q2 hfe equal 220. But if Q2 hfe is 120, then the gain will drop to about 1.45 * 155 = 224 V/V. The first stage gain is now around 1.45[V/V].

Also, you need to increase the values of the capacitors. Especially the C2 and C3 values.

C2 = 0.16/(6.5Ω * 20Hz) = 1200µF and C3 = 0.16/(0.58Ω * 20Hz) = 13000µF.

  • \$\begingroup\$ Could you explain why you equate the capacitor impedence with the emitter resistance to find the capacitor values? TIA \$\endgroup\$
    – AfiJaabb
    Jan 22, 2023 at 12:15
  • \$\begingroup\$ The emitter capacitors form a RC high-pass together with the transistor's emitter output resistance. At the cross-over frequency of a passive RC element, the (imaginary) impedance of the capacitor has the same magnitude as the resistor's (real) resistance. \$\endgroup\$ Jan 22, 2023 at 13:05

Old op schematics ...

I get a maximum gain of ~250

Here is a simulation with your values (except Q2 BJT model, R4 and R3).

I only get a gain of ~ 160 ...

enter image description here

With OP corrected schematic ... Capacitors changed for wide bandwidth.

enter image description here


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