In my application I will use a MOSFET as an on-off switch. There won't be a PWM signal. I want to calculate the temperature rise of the MOSFET but I am confused.

Continuous drain current is 100 A, RDS(on) is 3.2 mΩ, ambient temperature is 25 °C. In the datasheet junction-to-ambient thermal resistance is 62 °C/W, junction-to-case thermal resistance is 0.5 °C/W.

I have researched this subject and used the below equations, but they give me nonsensical results. What is the correct way of doing this calculation?


  • 3
    \$\begingroup\$ Looks good: It says, "you need a heatsink" \$\endgroup\$
    – glen_geek
    Jan 24, 2023 at 16:01
  • \$\begingroup\$ Heatsink indeed. Formula will be Ploss(Rthjc+Rthheatsink)=deltaT \$\endgroup\$
    – winny
    Jan 24, 2023 at 16:05
  • \$\begingroup\$ From the Rth(j-a), it looks like you're using a device in a TO-220 package. While these can have continuous drain current ratings over 100 A, that's more of a theoretical limit to avoid, say, melting the bond wires. I suggest using a SSR if possible since they are in packages designed to efficiently get rid of the amount of heat you're going to be producing and have very well defined thermal characteristics with standard heatsinks. A TO-220 package is entirely unsuited to this amount of current and will be almost impossible to heatsink properly. \$\endgroup\$
    – vir
    Jan 24, 2023 at 19:05

4 Answers 4


Yes the calculation is correct.

Using several transistors in parallel is probably the most beneficial. Heat sinks are bulky and expensive.

Since power is based on the square of the current, then reducing the current by 1/2 reduces the power dissipation by 1/4. So then using two transistors reduces the individual dissipation by a quarter and the total power by 1/2 making the overall system more power efficient.

There are FETS that have RDSon as low as \$0.25m\Omega\$.

I put together a spreadsheet that demonstrate the effectiveness of both paralleling FETs and choosing lower RDSon in order not to use a heatsink. I used \$T_a=50 ^0C\$ as the effective ambient temperature. It will be higher than the surroundings, being enclosed. The transistors must be mounted as per the datasheet to get the specified thermal resistance.

It shows how overall power efficiency can be improved by paralleling several FETs. This can also reduce the effective ambient temperature by reducing the power dissipation into the enclosure.

The spreadsheet is an example only. Every situation is different. For example, airflow can be used to reduce the thermal resistance.

The spreadsheet may help in choosing a thermal system.

enter image description here


Normally, you have 3 thermal resistances:

  • RTh-jc : Junction to case
  • RTh-cs : Case to to heatsink (case to soldering point, for SMD devices such as D²PAK)
  • RTh-sa : Heatsink (or soldering point) to ambient

So the final junction temperature becomes

$$ \mathrm{T_J=P_D \ (R_{Th-jc}+R_{Th-cs}+R_{Th-sa}) + T_A} $$

where PD is the total power dissipation and TA is the ambient temperature.

If there's no heatsink attached then you can simply use RTh-ja on its own for final junction temperature:

$$ \mathrm{T_J=P_D \cdot R_{Th-ja} + T_A} $$

For SMD devices RTh-ja may not always be given so the junction-to-soldering point comes into play.

it gives me nonsense result

No it doesn't. Let's see.

In your case there's no switching losses, so all the loss is conduction (I²R) loss : \$\mathrm{P_D=I_D^2 \cdot R_{ds-on}=32 \ W}\$.

Assuming no heatsink attached, final junction temperature becomes \$\mathrm{T_J=P_D \cdot R_{Th-ja} + T_A = 32 \cdot 62.5 + 25 = 2025 \ °C}\$ which is way beyond the absolute maximum ratings (probably somewhere between 125 and 150 °C). So the MOSFET will definitely require a heatsink.


The thermal characteristics are given with a specific layout and copper cooling area, and the use of a heatsink.

In your example your MOSFET has to dissipate 32 W (P = R × I² = 100 x 100 x 0.0032). This is really awsome, what kind of package can dissipate this power?

What is the maximum current rating of your transistor?

Maybe you should reconsider your choice and use another MOSFET with a lower RDS(on), or use multiple MOSFETs.


The junction-to-ambient rating of a part is for the part with no additional thermal paths to ambient except for itself. 62 °C/W is not unreasonable. While a 2000 °C rise in temperature is unreasonable, what that math is really telling you is that you'll turn on the part, get less than a second at 100 A, and then it'll send up a smoke signal that reads "shoulda used a heat sink".

The junction to case rating of a part is for the part with a perfectly thermally conductive bond to an infinitely large heat sink. In this case you could expect a 16 °C rise over the heat sink temperature.

There are good long discussions here and on other sites, but the short -- to the point of being inadequate -- description of the process is that you need to:

  • Decide on an ambient temperature. 25 °C won't cut it; things will always get warmer than that. I usually use 55 or 85 depending on whether there's humans around or not.
  • Subtract that ambient from the allowable junction temperature. That's your allowable temperature rise.
  • Divide that temperature rise by your anticipated power. That's your target thermal resistance.
  • Subtract the case-to-junction thermal resistance. What's left over is your thermal resistance budget.
  • Figure out the thermal resistance of your case-to-heatsink attachment method (metal-to-metal, mica washers, thermally conductive silicone, whatever). Subtract that -- what's left is the thermal resistance of your heat sink.
  • Go shopping for heat sinks. Find a manufacturer that lists them, or find a handbook that shows you how to calculate.
  • If you just can't get there from here, use multiple FETs or one with a lower RDS(on)

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