How does a D flip-flop stabilize?

Question

I am trying to understand how a flip-flop stabilizes internally after setting up, before the clock starts ticking.

I assume:

• An electric signal takes no time to transmit from one end of a wire to the other;
• A NAND gate takes 3 time units to generate output;
• A NOT gate takes 2 time units to generate output;
• All wires start with signal 0;
• D and CLK stay 0.

The states of all wires of first 20 time unit follows:

time	D	D'	CLK	T1	T2	Q	Q'
0	0	0	0	0	0	0	0
1	0	0	0	0	0	0	0
2	0	1	0	0	0	0	0
3	0	1	0	1	1	1	1
4	0	1	0	1	1	1	1
5	0	1	0	1	1	1	0
6	0	1	0	1	1	0	0
7	0	1	0	1	1	0	0
8	0	1	0	1	1	1	1
9	0	1	0	1	1	1	1
10	0	1	0	1	1	1	0
11	0	1	0	1	1	0	0
12	0	1	0	1	1	0	0
13	0	1	0	1	1	1	1
14	0	1	0	1	1	1	1
15	0	1	0	1	1	1	0
16	0	1	0	1	1	0	0
17	0	1	0	1	1	0	0
18	0	1	0	1	1	1	1
19	0	1	0	1	1	1	1

It is clear that Q and Q' are repeating a pattern with cycle length 5 and never stabilize. Is there any mistake with the assumptions I made? How does a flip-flop stabilize in practice?

(This question is a duplicate of https://stackoverflow.com/questions/75230504/how-does-d-flip-flop-stabilize. Will delete the other once one of them gets answered.)

Answer 1

First, this isn’t actually a D flop. It’s a gated D latch.

With that out of the way, it isn’t possible to predict which state this latch will power up in. It will randomly power up in either of two states, or even possibly in an in between (metastable) state.

The problematic assumption in your sequence is that T1 and T2 go high at exactly the same time. This, in theory, will lead to the latch going into oscillation.

That won’t happen. In the vast majority of cases, there will be a slight imbalance in the feedback, or in T1/T2 delay, which will tend to nudge the latch into one state or the other.

The imbalance can be in the circuit itself, such as unequal delay; or even external influences, such as stray electric fields or even an alpha particle hit.

This would be properly modeled using analog simulation as opposed to a digital one.

Answer 2

Here is a simulation circuit for "help" understanding the behavior of digital circuits with "delays".
Note the use of D-Edge FF (zero delays) for including some "controlled" delay through the 100 MHz clock (feedback signals _q1 and _q2 to inputs FF).

For example, here are two cases where some delays are 0 ns and others are TTL delays.
Interval of time of interest: When "gate" = 1.

Case U9 -> D0_gate, U10 -> TTL_gate.

Case U10 -> D0_gate, U9 -> TTL_gate.

And here, at a slower speed, the worst case response for all gates "TTL_delay".