I am trying to understand Flip Flops & Latches. I am reading from Digital Logic book by Morris Mano. One thing I am not able to understand is why we clock flip-flops?

I understand why we need 'enabled' or gated latches. But what’s the use of clock? I am not able to understand this. Why can't we just enable the required flip-flops & give them input? As we change input, the output changes. Why do we have to change the output with rising or lowering clock edge (in case of edge triggered flipflop)?

Any help regarding this is appreciated.


One reason we clock flip flops so that there isn't any chaos when the outputs of flip flops are fed through some logic functions and back to their own inputs.

If a flip-flop's output is used to calculate its input, it behooves us to have orderly behavior: to prevent the flip-flop's state from changing until the output (and hence the input) is stable.

This clocking allows us to build computers, which are state machines: they have a current state, and calculate their next state based on the current state and some inputs.

For example, suppose we want to build a machine which "computes" an incrementing 4 bit count from 0000 to 1111, and then wraps around to 0000 and keeps going. We can do this by using a 4 bit register (which is a bank of four D flip-flops). The output of the register is put through a combinatorial logic function which adds 1 (a four bit adder) to produce the incremented value. This value is then simply fed back to the register. Now, whenever the clock edge arrives, the register will accept the new value which is one plus its previous value. We have an orderly, predictable behavior which steps through the binary numbers without any glitch.

Clocking behaviors are useful in other situations too. Sometimes a circuit has many inputs, which do not stabilize at the same time. If the output is instantaneously produced from the inputs, then it will be chaotic until the inputs stabilize. If we do not want the other circuits which depend on the output to see the chaos, we make the circuit clocked. We allow a generous amount of time for the inputs to settle and then we indicate to the circuit to accept the values.

Clocking is also inherently part of the semantics of some kinds of flip flops. A D flip flop cannot be defined without a clock input. Without a clock input, it will either ignore its D input (useless!), or simply copy the input at all times (not a flip-flop!) An RS flip-flop doesn't have a clock, but it uses two inputs to control the state which allows the inputs to be "self clocking": i.e. to be the inputs, as well as the triggers for the state change. All flip flops need some combination of inputs which programs their state, and some combination of inputs lets them maintain their state. If all combinations of inputs trigger programming, or if all combinations of inputs are ignored (state is maintained), that is not useful. Now what is a clock? A clock is a special, dedicated input which distinguishes whether the other inputs are ignored, or whether they program the device. It is useful to have this as a separate input, rather than for it to be encoded among multiple inputs.

  • \$\begingroup\$ It makes sense when you explain need of clocking for counter or state machine. If there's is no clock at all, then the counter just keeps changing its value (&reset) & start infinitely ? and same with state machine. (From what I read from wiki, counters just a type of state machines, since the states are being changed). But even with registers also we use clock, in that case why ? I also want to know are there any flipflops (can be) used in any application without a clock ? \$\endgroup\$ – avi Apr 11 '13 at 4:44
  • \$\begingroup\$ Now coming to point of stability, if the outputs keeps changing then other devices which need flipflops output won't be able to receive it correctly and there could be erratic behaviour. So is this stability issue ? Now I am trying to understand the concept of stability. Especially these two paras you explained : "to prevent the flip-flop's state from changing until the output (and hence the input) is stable." "Sometimes a circuit has many inputs, which do not stabilize at the same time" \$\endgroup\$ – avi Apr 11 '13 at 4:45

A rising-edge flip flop may be envisioned as two latches back to back, one of which is enabled shortly after the clock signal goes low and remains enabled until it goes high; the second is enabled shortly after the clock goes high and remains enabled until it goes low. Having a brief moment during which neither flip flop is enabled means that the output of a flip flop may be safely fed back to its input via combinatorial logic. A change to the output on one clock cycle may cause the input to change, but that input change won't have any effect until the next clock cycle.

Historically, it used to be pretty common for digital devices to use what was called a "two-phase clock", which had two clock wires which were high for non-overlapping intervals during each cycle. All of the latches are divided into two groups, with one clock controlling the first group of latches and the other clock controlling the second; in most cases, the outputs of each group are only be used to calculate the inputs of the other. Each clock cycle consists of one or more pulses on the first clock, at least one of which must meet minimum-length specs, and one or more pulses on the second (same requirement). One advantage of such a design is that it can be very tolerant of clock skew provided that the dead time between clock phases exceeds the clock skew amount. Two disadvantages of such designs are that they require running two clock wires all over the place, and that to obtain maximum speed one must generally partition the logic into two groups and try to balance the propagation delays between them.

A more "modern" approach is to have every latching element (register) receive a single clock wire and essentially generate its own internal non-overlapping clocks. This requires that the maximum clock skew not exceed the minimum propagation time between registers, but modern tools make it possible to control clock skew more precisely than was possible in decades past. Further, in many cases, single-phase clocking makes designs simpler by eliminating the need to partition the logic into two groups.


We all know that digital real circuits are going to contain a LOT of gates. A signal may have to take multiple paths to get to the last gate that gives the output. A signal takes some amount of time to "propagate" on the different paths reaching the last gate. The time taken to propagate is not the same on different paths. This leads to what we call as glitches. Glitches occur since some paths are shorter than others and when a signal reaches the last gate earlier taking the shorter path it effects it immediately before the other signals on the longer path reach the gate. The output that this results in momentarily is wrong and can become dangerous in a digital circuit leading to errors propagating.

Now I come to why we need a clock. A clock essentially "synchronizes" the circuit to a single external signal. Think of it as a beat that the circuit is tuned to like music. Things happen in tune with this clock, no clock = circuit is disabled. By using clock we make sure that the different parts of the circuit work in harmony at the same time. This way the behavior of the circuit is more predictable. It is also less effected by changes in propagation delay by temperature and manufacture variation. This covers the clock.

Flip flops are such digital circuit elements that take an action (changing their output in response to an input at their input port) when a "CLOCK EDGE" occurs. Clock edge is when the clock signal goes from 0 to 1 or from 1 to 0. Just draw a clock wave and you will know what I mean. There are another group of elements called latches, the output of latches change to reflect the input when a certain control signal is at a specific logic LEVEL and don't wait for any edges, this control signal is called ENABLE in latches. Latches may work when enable is 1 and change their output or when enable is 0. It depends on the latch type. In contrast Flips flops actually do something only when they are fed by a clock EDGE. Please note this difference between latches and flip flops, and remember that latches are connected together to create a flip flop such that the enable only causes the flip flop to do something when a clock edge occurs. In this case we name the Enable signal to Clock, and its make more sense as well. The clock for humans goes tick tick tick, the flip flop does something only at ticks and NOTHING in between the ticks.

If it is still not clear than you will benefit by watching the nptelhrd lecture on youtube from Indian Institute of Technology on Digital Circuits.

  • \$\begingroup\$ "By using clock we make sure that the different parts of the circuit work in harmony at the same time. " - how do we do this ? I will check out the videos. \$\endgroup\$ – avi Apr 11 '13 at 3:32
  • \$\begingroup\$ Please note that the flip flops are devices that change their output to reflect the input at the rising edge (or the falling edge if it is a negative edge triggered flip flop) of a control signal for a positive edge triggered flip flop. This control signal is called a clock due to its periodic nature, more like the tick-tick of our wall clocks. If clock signal is present the flip flop will do something, otherwise the input will not make anything happen to the output. Please know the difference and similarity between latches and flip-flops from an early stage also so as not to be confused. \$\endgroup\$ – quantum231 Apr 20 '13 at 20:43

There are such things as asynchronous counters. Here's one: - enter image description here

It's also known as a ripple counter because when an input pulse arrives at the input (changing the state of the 1st flip-flop), that change of state takes a finite length of time to ripple thru to the remaining flip-flops. During that small but finite length of time the outputs ABCD will have an unpredictable transient value until the final flip-flop has settled.

If the outputs ABCD were then all fed through D type flip-flops and clocked together, some time after the settling period, this "better" version of ABCD will never "display" this transient behavior.

To avoid this engineers sometimes use synchrounous clock circuits. Sorry the input is from the left on this one and Q0 to Q3 map to ABC and D on the previous diagram: -

enter image description here

It's a little more complex but it's quicker and has fewer parts than compared to an asynch counter with a bunch of D types on the outputs.

  • \$\begingroup\$ Well, with counters it makes sense. But is there any application where flipflops are used without clocks ? or flipflops can never be used without clocks ? \$\endgroup\$ – avi Apr 11 '13 at 8:11
  • \$\begingroup\$ @avi The first example (async counter) doesn't have to be regarded as taking its input from a "clock". It could be pulses coming from a magnetic sensor looking to see how fast a shaft rotates. There would be a "master" clock on the system that "gates" the count every second but the "signal" going into the counter isn't necessarily a clock. The output from an analogue comparator could "clock" a "1" to the output of a D type and the output from another analogue comparator can reset the D type - this can be used to produce a signal derived from an analogue waveform - no clocks as such \$\endgroup\$ – Andy aka Apr 11 '13 at 8:41
  • \$\begingroup\$ I would regard the behavior of a ripple counter as being quantitatively rather than qualitatively different from that of the synchronous counter. The outputs of both counters will become invalid some period of time after a clock pulse arrives, and will become valid again some period of time after that. The synchronous counter will have a smaller window during which its outputs are invalid, but the window will be non-zero in any case. It's also worth noting that the maximum count speed with the counter as drawn will be limited by the counter length. One could avoid that limitation... \$\endgroup\$ – supercat Apr 11 '13 at 16:40
  • \$\begingroup\$ ...by having the carry chain start at e.g. the fourth bit, generating the "and" of the first three bits, and then having each bit only flip if the input from the carry chain was high, bit 2 was high, bit 1 was high, and bit 0 was high. Even if seven count pulses arrived in time required for a signal to propagate through the carry chain, that would be no problem since the carry chain would start propagating the carry when count xxx111...111000 was reached but its output wouldn't matter until the clock pulse after xxx111...111111 was reached. \$\endgroup\$ – supercat Apr 11 '13 at 16:46
  • \$\begingroup\$ Them ripple counters are simple but detested in the real world of digital circuits that I work in. Its good to know that they exist but it is highly unlikely that you will be allowed to use them for real projects. It can always be used in trivial exercises where their "asynchronous" nature is not an issue. \$\endgroup\$ – quantum231 Apr 20 '13 at 20:45

Because its easier to design synchronous systems (synchronous system means any collection of combinatorial logic and clocked flip-flops) than asynchronous systems, and synchronous systems are more reliable. However, asynchronous state machine design is worthy of study because it can compute an output much faster and with lower power than a synchronous system.


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