ADC data sheets (one example below) state that the differential input of A/D can span between -Vref to +Vref. Yet when it's single ended it only spans 0 to +Vref.

If a differential input can swing Vref around 0 V thus having a peak-peak swing of 2×Vref, then why in single-ended it can't swing Vref around Vcm so it still has 2×Vref peak-peak input range? (Assuming the input transistors are biased such they can tolerate those voltages.)

Below illustration from TI ADS1194 might be useful to those who can explain the reasoning.

enter image description here

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    \$\begingroup\$ In both cases you're swinging around Vcm, not around zero. In the single ended case, if the maximum voltage range is Vref, then you cannot feed in 2*Vref because that's twice the allowed voltage for each input. \$\endgroup\$ Jan 30, 2023 at 0:42

2 Answers 2


If a differential input can swing Vref around 0 V

No, this is not what your two diagrams are showing.

The one signal voltage in the single-ended diagram is swinging around the common mode voltage. Each of the two signal voltages in the differential-input diagram is individually swinging around the common mode voltage as well. Nothing is swinging around 0V, where 0V is defined as ground.

And whenever I say voltage at a point, I mean the potential difference between that point and ground. So one of the signal voltages, measured relative to ground, is swinging about the common mode voltage, measured relative to ground. You cannot say the difference between the two signal voltages in the differential input diagram is swinging about the common mode. That doesn't make sense. You can say the two input signal voltages swing around each other (implying measuring each one relative to a common third node), but it doesn't make sense to say their difference swings around some third voltage, because you are already taking a difference of the two input voltages before introducing the third voltage. Doing so would be like saying the difference in altitude between two airplanes relative to the sea level. Makes no sense.

Assuming the input transistors are biased such they can tolerate those voltages

Except you can't assume this because then you're using a completely different ADC altogether. This is like saying asking "Why can a car not carry as much cargo as a truck? Assume both vehicles are large enough that the cargo can fit inside."

It comes down to the fact the ADC was designed such that each individual input cannot accept a voltage higher than Vref relative ADC's ground pin. This is called the "absolute input range" of each pin. This has an impact on the "dynamic range" which is the range of the voltage signal that the input pins A and B can read together.

You cannot ignore the voltage difference between each individual input pin and the ADC's ground pin. The voltage between the two input pins is not the only voltage that matters.

For example, suppose we have a differential ADC with input pins A and B where the absolute input range of the input pins relative to the ADC's ground pin is:

\$ V_{ref}-V_{gnd} \ge V_A-V_{gnd}\ge V_{gnd} \rightarrow V_{ref} \ge V_A\ge 0V\$

\$ V_{ref}-V_{gnd} \ge V_B-V_{gnd}\ge V_{gnd} \rightarrow V_{ref} \ge V_B\ge 0V\$

Let's also assume that for this ADC, the maximum and minimum differential voltage between the input pins is.

\$ V_{ref}-V_{gnd} \ge (V_A-V_{gnd})-(V_B-V_{gnd})\ge V_{gnd}-V_{ref}\$

\$\rightarrow V_{ref} \ge V_A-V_B\ge -V_{ref}\$

This means that for this ADC you can have pin A be at the max absolute limit and pin B at the min absolute limit and have a valid reading. But this will not necessarily be true on every ADC. It might such that even within the absolute input range of each pin, the voltage between input pins is only valid if they are close enough together No damage, but not valid.

If we wired this up in a single ended setup then by definition this means that \$V_A\ge V_B\$ is always true or \$V_A\le V_B\$ is always true. For this example let's say it is \$V_A\ge V_B\$. Then it would mean that our dynamic range is at most

\$\text{Max S.E. Dynamic Range}=V_{max}-V_{min}=(V_{Amax}-V_{Bmin})-(V_{Amin}-V_{Bmax})=(V_{ref}-V_{gnd})-(V_{gnd}-V_{gnd})=V_{ref}\$

Exceeding this results in the absolute input range on one or both of the input pins being exceeded.

And in your block diagrams the dynamic range is less than this maximum since \$V_b\$ is not \$V_{gnd}\$; It is a \$V_{CM}\$ which is a more positive number.

But when wired up in a true differential set up, then between both \$V_A\ge V_B\$ and \$V_A\le V_B\$ are allowed. Now your dynamic input range is

\$\text{Max D.E. Dynamic Range}=V_{max}-V_{min}=(V_{Amax}-V_{Bmin})-(V_{Amin}-V_{Bmax})=(V_{ref}-V_{gnd})-(V_{gnd}-V_{ref})=2V_{ref}\$

Yet the absolute input range on your input pins has not changed.


In the first case, the full swing is +1/2VREF+VCM on half cycle, and VCM-1/2VREF on 2nd half of cycle, so +1/2VREF+VCM -(VCM-1/2VREF) = VREF pkpk full swing differental input.

In the second case, you have two signal swings being processed fully differentially. On first half cycle it is +1/2VREF - (-1/2VREF)+VCM, 2nd half it is (-1/2VREF - 1/2VREF +VCM), or subtracting first minus second +VREF +VCM - (-VREF +VCM) = 2VREF pkpk full swing differential input.

That's one of the benefits of fully differential signaling, you get double the swing. Yet, the input circuit itself only needs process one full range of one of the single ended full swings, it is just doing it differentially in the second case, requiring no additional headroom constraints on the circuitry.


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