As a development to my previous question I am developing a protocol to drive VGA through lines originally designed for SPI communication.

The problem is that I may be able to instruct the receiving decoder to have either VSYNC, HSYNC or color. This means I can't perform HSYNC during VSYNC. To my understanding no RGB color information during HSYNC or VSYNC should not be a problem.

Searching for information I can't find any trustworthy source of info to decide if VSYNC without HSYNCs will work with all VGA monitors. Most sources compare HSYNC or VSYNC to picture/color frame, the only place I found something material is here.

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This clearly shows that there are HSYNC pulses during the VSYNC pulse, but there's no clue if it is someone's assumption that it always must be this way per specification. Referenced link to datasheet of ADV7125 does not help much.

I would expect there is no vital need for HSYNCs while VSYNC is in progress, but would love to see any trustworthy source confirming or disproving this assumption. Any help would be greatly appreciated.

  • \$\begingroup\$ During the VSYNC low, the top and bottom "borders" are being "drawn". I guess the rationale of having HSYNC during that time is to place the cathode ray in the proper defined position in the beginning of the next frame. \$\endgroup\$
    – Eugene Sh.
    Jan 30, 2023 at 17:32
  • \$\begingroup\$ @EugeneSh. more specifically, VSYNC edge triggers vertical flyback. It happens after bottom border, and it also ends before top border is drawn. And the CRT would loose HSYNC if it is not sent so it is required regardless of VSYNC. A CRT has both horizontal and vertical drives, they don't really know or care what the other drive is doing as long as they get their own sync. \$\endgroup\$
    – Justme
    Jan 30, 2023 at 17:41
  • \$\begingroup\$ @Justme Well, I guess the question boils down to "why can't we "stop" the horizontal drive in the end of the last visible line and restart after the vertical retrace? Why do we need it to "draw" invisible lines? \$\endgroup\$
    – Eugene Sh.
    Jan 30, 2023 at 17:46
  • 2
    \$\begingroup\$ @EugeneSh. Answer to that could fill a book, but the HSYNC may be used for flyback transformer which generates the HV (IBM 5151) so it would stop HV generation. In a TV which will free run at some slower rate without HSYNC as PLLs were not really a thing, it would drift out of sync and it would take several lines to catch up again to be in sync. Besides the HSYNC is used at source to count lines of video, and so at sink end it can be used to count lines to detect video timings. Video is expected to be a continuous stream of data. Some TFT interfaces do work with a single Data Enable signal. \$\endgroup\$
    – Justme
    Jan 30, 2023 at 18:02
  • 2
    \$\begingroup\$ "The problem is that I may be able to instruct the receiving decoder to have either VSYNC, HSYNC or color." - why can't one of the instructions be HSYNC with VSYNC? VSYNC never occurs by itself. \$\endgroup\$ Jan 30, 2023 at 22:59

3 Answers 3


I can't find any trustworthy source of info to decide if VSYNC without HSYNCs will work with all VGA monitors.

We only have to find one example that doesn't work to prove the negative, so...

I made a circuit that suppresses HSYNC during VSYNC, and inserted it inline with the VGA cable. With suppression active My LCD monitor didn't think a signal was present. So the answer is no, it doesn't work with all VGA monitors.

However when I plugged in an old CRT VGA monitor it worked fine with no visible effect, so some monitors may be OK with it.


Yes, HSYNC is required. The monitor loses horizontal sync if you stop sending it, regardless of the state of VSYNC.

Or, if the receiving thing is not directly a monitor but some chip that samples analog VGA. Or a digital link of some sort.

The assumption is that a video signal is continuous. VGA card generates a continuous HSYNC, and other preceeding IBM PC standards like EGA, CGA, and MDA did, and also television signals did. Generally CRTs of that era expected it. Certainly the IBM 5151 monitor for MDA did, as the HSYNC signal was directly driving the horizontal flyback circuitry which also generated the high voltage used to drive the electron gun, so omitting it would not be expected.

Devices generate both sync signals continuously, as it is the simplest method to just run a line counter from HSYNC to generate VSYNC timings.

A CRT monitor from VGA era would also expect to have continuous HSYNC, as the horizontal and vertical circuits to scan the beam may be completely separate analogue circuits that both handle their jobs separately.

A digital monitor that supports multiple resolutions would have an MCU which counts the lines from HSYNC pulses so the measurements would be off if HSYNC is not continuous.

Video formats and interfaces are also defined with the assumption that HSYNC timing always holds for all lines, regardless of VSYNC state.

Some equipment might tolerate a missing HSYNC, but it will always work with all equipment if you do send continuous HSYNC.

I guess there is not much info what would happen if you tried to skip HSYNC during VSYNC, as I can't think of any reason why would any device attempt to do so. But now in another answer, it is proven that not all displays show a picture when HSYNC is suppressed.

  • \$\begingroup\$ "directly driving the horizontal flyback circuitry which also generated the high voltage used to drive the electron gun, so omitting it would not be expected." - there is also a warning hidden in this. Trying to be clever with sync signals can upset this kind of circuitry, and some 1980s and 1990s era monitors are known to be easily permanently damaged if that happens. \$\endgroup\$ Feb 1, 2023 at 9:21
  • \$\begingroup\$ @rackandboneman This is true, programming the HSYNC (and/or VSYNC) accidentally or on purpose to incorrect frequency, duty cycle, or polarity may actuallly have damaged the monitor, so I also don't think they were just urban legends. \$\endgroup\$
    – Justme
    Feb 1, 2023 at 11:25

If you have a receiving decoder you get to do whatever you want: it’s no longer VGA, it’s a digital video link. You could for example produce H sync all the time (with SPI CS, say) and encode the data immediately following as flags for H, V and possibly F (field). Think of it as a poor man’s BT.656 with just three bits instead of 8. This could be decoded into RGBHV with a CPLD.

(Video hint: code your lines as half-lines so you can support interlace.)

If your intention is to drive any legacy VGA (analog) display, TTL H and V sync are both necessary. This is defined by the VESA spec and all VGA monitors support it as a baseline.

Some VGA monitors support combined H and V sync, sent either as sync-on-green or as a separate TTL, either way following RS-170 standard.

On the other hand, suppressing H sync during the vertical interval is definitely not standard. CRT monitors expect continuous H sync to make retrace and run the flyback. Digital monitors (LCD, plasma, etc.) use H sync for clock recovery. It’s highly unlikely that you’ll find a modern monitor that will work without seeing a consistent H sync.


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