I've eventually replicated the ideal diode as described in this schematic using a matched transistor pair.

enter image description here

It seemed to be working fine at first, but my VDS is around 6-700 mV at only 8 A which is nowhere near where it should be.

So I started investigating and it seems my VGS is only 60 mV which would explain the very high RDS(on), but I can't think of a good reason why.

Here is the schematic I used to route my PCB. I doubt it is of great interest given it's an exact copy of the one above, but I'm including it for the sake of completeness:

enter image description here

I've also replicated the op-amp schematic and I also get 6-700 mV VDS @ 8A.

enter image description here

Any lead I could follow?

  • \$\begingroup\$ Is the direct connection from Q1a base to collector by intention? This looks a bit strange. Anyway, the transistor Q1b turns on and therefore the voltage on it's collector is only Vce away from "Out" and this is what you get on the gate. It functions like it is wired, but the wiring is odd. \$\endgroup\$
    – datenheim
    Commented Jan 30, 2023 at 18:52
  • \$\begingroup\$ Have you made sure that anyone has ever built the circuit you cite and had it work properly? Lots of such circuits out there that get written up with only a cursory look and they never have in fact worked. Not sure about this one. DMMT3906W is two dies on one leadframe so while the production process does the selection, it's not as good as an integrated pair would be... \$\endgroup\$ Commented Jan 30, 2023 at 18:52
  • \$\begingroup\$ It would help to note that the diagram and waveforms you show are from someone else's simulation. So, have you actually simulated it yourself? If so, post your results. Have you built it yet? Otherwise it's all a bit of a theoretical discussion... \$\endgroup\$ Commented Jan 30, 2023 at 18:57
  • 1
    \$\begingroup\$ @datenheim With IN<OUT, Q1b is turned on. With IN>OUT, Q1b turns off since the B-E diode gets reverse-biased. R1 and R2 are different and that's probably where most of the problem lies. This circuit needs a better "current mirror". At least there needs to be a third transistor that buffers the base potential so that the left branch isn't loaded more than the right branch. That's why R1 is smaller than R2. This circuit, to work properly, must have identical R's, and then the topology has to be improved until it starts working. I doubt very much that it got any real-life testing in a circuit. \$\endgroup\$ Commented Jan 30, 2023 at 19:12
  • 1
    \$\begingroup\$ @VoltsAndNuts Please don't use the "AOP" acronym. It's meaningless to most people. And please just post your own results and schematics. You say that you "replicated it". I don't see anything of yours here, so maybe your replication has a problem? How could we tell. Show the circuit you have tested/simulated, not someone else's pictures. Until the pictures are yours, there's no way we can help with your problem. Perhaps there's a trivial mistake in your schematic that we can see but you are missing. That's why it's so important not to just say "I replicated" without showing your work \$\endgroup\$ Commented Jan 30, 2023 at 19:14

2 Answers 2


The issue is that your Vgs limits how hard the FET can be turned on. With a more-negative reference for the BJT pair the Rds(on) improves.

Here's a quick sim to demonstrate the effect (simulate it here):

enter image description here

As you sweep the current mirror bias between 0 and -10V, you'll see Vgs increase and Vds decrease.

  • At 0V bias, Vds drop is -277mV
  • At -10V bias, Vds drop is -60mV

In this sim FET 'beta' is set to 15. Modify as appropriate for your target FET, using the worksheet at https://www.falstad.com/circuit/mosfet-beta.html

As it is, the IRF7404 is rated at -6.7A @ 25 deg.C, so 8A is really more than this FET can handle. Nevertheless, to achieve the max low 'forward' ideal-diode drop it needs more Vgs drive.

FET link: https://www.infineon.com/cms/en/product/power/mosfet/p-channel/irf7404/


There are some problems with the original circuit, the primary one is low gain and biasing as-if this was a current mirror, where - instead - a differential pair biasing is called for.

It also won't work at such a low voltage due to the Vgs(th) of the PMOSfet. A microcurrent oscillator and a charge pump would be needed to fully turn on the mosfet at single-cell voltages. Parts of this circuit could also be redesigned using small-signal mosfets - I'll revisit that later.

We essentially want a comparator built out from a differential pair. If such a comparator is driven from low impedance nodes, the drive voltage can be equivalently provided on the emitters or on the bases. That's what this circuit does.


simulate this circuit – Schematic created using CircuitLab

A differential pair with emitter inputs only needs a bias current on the bases. R5 takes care of it. R3 and R4 suppress positive feedback across the comparator, with R5 acting as a long tail load, "reflected" to the common base node instead of the common emitter node. That's why R5 can be pretty large: its conductance is multiplied by the current gain of the pair, acting as-if it was at the common emitter node.

R6 decreases the gain of the left leg of the differential pair when the diode is turned on.

Some compensation will be necessary if R9 is much larger (say 1k or more).

This circuit was built and performs reasonably with right side at 5V and left side between 0V and 10V.


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