0
\$\begingroup\$

I need your help here. One of the SiC MOSFETs (SCTH70N120G2V-7) on top is getting hot as I increase the voltage for boost testing with a 50% duty cycle circuit. I cannot understand why my MOSFET is getting this hot since the MOSFET I am using is rated for 1200 @ 90 A. When I measure the temperature with 2 A at the output and a load of 100 Ω, it shows 85 degrees. That is close to killing it. When I increase the voltage to 200 V with an output of 400 V at 4 A, one of the MOSFETs just dies. I am using a UCC5350MCDWVR gate driver to drive it.

enter image description here

Layout:

enter image description here

enter image description here

The last picture is Vgs for the two top mostfet. I using a isolated dc/dc supply (RA3-122005D/SMD) to power the gate drive.

\$\endgroup\$
5
  • \$\begingroup\$ Show Vgs and Vds oscillograms. How do you bootstrap your gate drive for the top devices? \$\endgroup\$
    – winny
    Jan 31, 2023 at 10:57
  • \$\begingroup\$ Both top mosfet share the same gate drive (UCC5350MCDWVR). The Rg_on is 2.7R and Rg_Off is 1R. \$\endgroup\$
    – ikenna
    Jan 31, 2023 at 11:02
  • 2
    \$\begingroup\$ How do you bootstrap it? Show Vgs and Vds waveforms. \$\endgroup\$
    – winny
    Jan 31, 2023 at 11:16
  • \$\begingroup\$ (Vgs for the two top [MOSFET] directly from the gate and driver source terminals using a divider probe, hopefully.) (Just musing: What if the inductor had two windings, each connected to one top/bottom MOSFET each? Two separate inductors got to be more effort, still, more costly or not. and would probably need antiparallel diodes between the drain/source/inductor junctions. Sort of difficult to lay out, and incompatible with the current layout.) \$\endgroup\$
    – greybeard
    Jan 31, 2023 at 17:34
  • \$\begingroup\$ Show Vgs and Vds in the same oscillogram. Just the one MOSFET which is failing. \$\endgroup\$
    – winny
    Jan 31, 2023 at 23:01

1 Answer 1

0
\$\begingroup\$

SiC FETs can turn on incredibly quickly. When designing a board with paralleled FETs it is very important to create a symmetrical gate drive for both FETs. What I see when I look at the layout you posted is a FET GD hitting one FET, then going through a via, under the first FET, and ending up at FET number 2. Furthermore, I do not even see the gate driver near these devices. Maybe show a wider view of the gate drive circuitry.

The vias and extra trace length cause an increase in inductance which creates a low pass filter. What is probably happening (unless winny is correct in the bootstrap thoery, which you should also check) is that the top FET is turning on before the bottom FET causing all of the energy to flow through one FET for a brief period before the second FET turns on itself.

For the bootstrap, as you increase load, your duty cycle will increase. This means that the top FETs will be on longer. The bootstrap capacitor that powers the top FET (unless you're using an isolated DC/DC to power the top side) has a limited amount of charge. When duty cycle increases this charge could be depleting which would cause the FET to operate with a much higher RDson than nominal.

\$\endgroup\$
1
  • \$\begingroup\$ That would be my suggestion as well. Inductance is a killer in this kind of application, and both the vias and trace lengths look suspect. Suggest direct probing of gate voltage at each fet and comparing. \$\endgroup\$
    – colintd
    Feb 2, 2023 at 23:42

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.