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I'm debugging a 1970s bitmap video generator board, and potentially among other issues it's not syncing happily to the old B&W video monitor I'm using (which is quite forgiving). The NTSC video signal it is currently putting out seems trivial: horizontal sync and vertical sync segments and black-level voltage for everything else. My understanding is this should simply result is a properly-synced, black screen.

My current concern is the horizontal sync pulses, which are only about 3.1uS in duration. The theory of operation for the board says that these should be 4uS, and although a hard statement of standards is elusive, my understanding is that most NTSC sources do more like a 5uS sync pulse. But I don't know how to think about adjusting it.

The circuit uses a 555 timer and 60Hz line voltage as reference to generate the line clock. (Schematic info is below.) That waveform looks like this, and that frequency can be adjusted with a variable resistor (R12 on the schematic linked below):

enter image description here

That signal enters a small bit of logic built around a couple 7400 NAND gates, and out comes this signal, which is supposed to be the 4uS hsync pulse (but which is actually 3.1ish microseconds):

enter image description here

  1. My confusion/learning question here is: can someone assist me in understanding how this bit of circuitry turns the first waveform into the second one? What is governing the time constant of the pulse length? Changing the line clock timing changes the distance between sync pulses here but the sync pulse width is pretty well fixed, and I can't really figure out where that duration is emergent from. (You can ignore the J2 connection point, it's unused.) This is what's actually on the PCB (the gates are labeled IC17b and IC17c); the schematic (linked below) appears to be the victim of scanning glitch for this section:

enter image description here

  1. Is anyone who knows video well able to clarify whether the 3.1uS sync pulse is actually not a problem and perhaps my sync issue lies elsewhere? The quality of the signals seem fairly poor/fuzzy but I don't know if that's a different or non problem.

The schematic for this board is here-- but note that the section of the PDF which contains this sync generation logic above with the pair of NAND gates (just below the center) suffers from a scanning (?) glitch, my drawing above is what's on the board. The theory of operation (p14) and plenty of other information is here and here. The theory states regarding this function:

The output of IC1 [the 555 timer] is fed via inverter IC23c to IC17b and c where among other things a 4 microsecond horizontal sync pulse is generated.

Thanks.

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  • \$\begingroup\$ Follow the logic of the diagram. What function are the gates performing together? What would happen if one input were delayed with respect to the other? Finally, what resistor and capacitor (R * C has units of time!) in the circuit could produce such a delay? Exact timing depends on component tolerances, drive strength and input threshold, but this gets you all the proportions, and the circuit is off by, at most, a constant. \$\endgroup\$ Feb 3, 2023 at 5:53
  • \$\begingroup\$ It helps if you draw the schematic horizontally. The circuit is known as a monostable or ‘one shot’. \$\endgroup\$
    – Kartman
    Feb 3, 2023 at 11:59

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What is governing the time constant of the pulse length?

This is determined by the time it takes for the capacitor on pin 4 of NAND gate IC17b to charge up through the resistor(s) to a voltage high enough for the gate to see it as logic '1'. When this happens the output of IC17b goes low, terminating the 'negative' sync pulse output of IC17c (lower gate in your diagram).

TTL logic gates do not have a well defined threshold voltage, so the timing could vary significantly between individual ICs. If you think the pulse should be longer then you could add some capacitance across C16 to slow down the charge rate. An extra 5 nF should stretch it from 3.1 μs to ~4.7 μs.

Is anyone who knows video well able to clarify whether the 3.1uS sync pulse is actually not a problem

For NTSC the normal horizontal sync pulse width is 4.7 μs. However during the vertical blanking interval extra equalizing pulses are added, so to keep the ratio of pulse to line width the same they are reduced to 2.35 μs.

Here is a timing diagram showing the area around the vertical blanking pulse (taken from the LM1881 Video Sync Separator datasheet):- enter image description here

The receiving equipment should be designed to work with a considerably shorter pulse width, but how much smaller would depend on the particular equipment (one video decoder chip I looked at had a minimum detection time of 1 μs).

Your circuit appears to produce fixed width pulses, so I guess 3.1 μs is a reasonable compromise. However it's not clear to me whether it produces correctly timed (or any) equalizing pulses. If it doesn't then this might explain why your monitor is not syncing to it properly.

In your previous question the video signal showed severely distorted sync pulses. Before playing with the timing you should make sure that the video waveform is clean and has correct levels when properly terminated.

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  • \$\begingroup\$ I appreciate this (yet again) Bruce-- you have a nice way of explaining and a clear way of writing. I'll go back to the signal investigation, this question really was mostly to understand that bit of circuit. The two resistors-- are they designed to be acing like a voltage divider for the non-delayed input? I'm fuzzy on RC circuits you've helped pinpoint. Thanks for the diagram with the timing indicated. During the vertical blanking, I'm pretty sure this just pulls the output to the low sync level for the whole vertical blanking time period, I don't think it's creating equalizing pulses. \$\endgroup\$
    – BZo
    Feb 3, 2023 at 19:29
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    \$\begingroup\$ The top resistor is probably just a pullup to get higher charging current and more stable timing (TTL outputs can't source much current, and get weaker when the voltage goes over ~3.5V). \$\endgroup\$ Feb 3, 2023 at 19:35

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