In general, when placing decoupling capacitors in parallel, their capacitances add and their compound ESR is reduced (like for parallel resistors). But I am a bit uncertain if/how this applies to their inductance, which is the most crucial aspect in high frequency decoupling.

The inductance of the decoupling current is usually given by its loop, set up by the delimiting planes/vias/capacitor leads. The following scheme is usually shown to understand the inductance of a decoupling capacitor (image from p.17 here):

enter image description here

So far so good. Now the same document also shows a suggested lateral placement of several capacitors on p.16:

enter image description here

This document is of course not alone with these suggestions. It is a general practice that I have seen many times. Maybe what makes this reference slightly more relevant is that it doesn't focus so much on ripple current capacity, but really on the loop inductance of the input capacitance.


If several (\$N\$) capacitors are paralleled, then - regardless of how many - the first image above always holds, i.e. the entire decoupling current still has to travel around the entire blue loop. The document is right to note that the current in Layer 1 and Layer 2 is opposite creating low inductance (aka: a small loop area), but the current through all the capacitors is still in parallel, so there is no flux cancellation from paralleling those capacitors and hence no inductance reduction. Correct?

Another related aspect: When I place the capacitors with much greater mutual separation (probably not practical), the first figure (cross-section) still holds, but their magnetic field coupling is reduced. In that case, one could argue that each capacitor has the loop inductance given by the blue loop in the image. But because there are now several independent such loops their impedances are in parallel. That argument would suggest that inductance is reduced to \$L_\text{loop}/N\$.

So is it actually clever to try to scatter the capacitance over as wide an area an possible, while still of course minimizing the individual loops as a primary goal?


2 Answers 2


I think the problem is the first drawing is only 2D so when looking at the cross section of the PCB, you only see the cross-section of the loop. However it also has another dimension, which would be its width when seen from the top in the second drawing.

Wider conductors have much lower inductance than thinner ones. A loop made of wide conductors stacked on top of each other (ie, copper pour over plane or wide trace over plane) will have inductance roughly inverse proportional to width. Caps are part of that loop too, and too few caps create a bottleneck reducing width.

So by putting several caps in parallel you don't change the cross section of the loop, but you increase the width of that loop. Thus inductance is reduced.

Some manufacturers offer "reverse geometry" caps like 0306 instead of 0603, these have lower inductance due to being wider and the electrodes closer together, but will they be in stock?...

If the two caps on the right are big enough you can put vias under them (#1 on drawing below) to reduce their inductance. If you think about the cross section you'll see that removes a little bit of the thickness of L1-L2 prepreg.

enter image description here

#2 shows the loop if the caps are placed in the "logical" "intuitive" place, this would probably turn out with more surface area and worse inductance than the suggested placement.

I've seen appnotes where half the caps are flipped to cancel the magnetic field. This seems to work but it makes a lot of holes in your top copper pour for ground vias, which makes it narrower, so higher inductance: in this case it would probably not work well. It was suggested for plane to plane decoupling, in this case the cap has 4 vias anyway.

  • \$\begingroup\$ Wider conductors have much lower inductance than thinner ones. And only with this being true, do all these usual practises, like inverted geometry caps, make any sense. That is what my intuition somehow tells me, too. But I can't recall any of the simple online "loop inductance calculators" that ever took this into account. Do you have a link that discusses it ? Because the loop inductance formula indeed does not reflect this. \$\endgroup\$
    – tobalt
    Commented Feb 3, 2023 at 10:53
  • 1
    \$\begingroup\$ yes, the calculation for "loop inductance" usually assumes cylindrical wires, and makes an approximation that wire thickness is small relative to distance between wires (loop width) so it works well for something that looks like an inductor (wire wound around a core) but not in this case! Here's an example: emisoftware.com/calculator/biplanar ; if you use the "trace over plane/microstrip inductance" formula and make the approximation that prepreg thickness is small relative to trace width you'll get the same value. \$\endgroup\$
    – bobflux
    Commented Feb 3, 2023 at 11:17
  • 1
    \$\begingroup\$ Basically plane/plane inductance is "per square", a 1mmx1mm square has the same inductance as a 1cmx1cm square ; this approximation does not account for the inductance of the via, pin, or other connection between component and plane of course. \$\endgroup\$
    – bobflux
    Commented Feb 3, 2023 at 11:20
  • \$\begingroup\$ Nice thank you. So I think that these parallel caps make sense because their width is already much wider than the loop height (prepreg thickness ~ 0.1 mm). So the magnetic field coupling is already not so strong, even when they are placed directly adjacently. Still it seems to be appreciable enough for manufacturers to even consider making stuff like IDC and X2Y caps. \$\endgroup\$
    – tobalt
    Commented Feb 3, 2023 at 11:24
  • \$\begingroup\$ The peculiar electrode shape of IDC/X2Y caps is great for reducing the inductance of the vias because it cancels the magnetic field. \$\endgroup\$
    – bobflux
    Commented Feb 3, 2023 at 13:30

Yes. Roughly speaking, inductance is proportional to [trace] length and [substrate] height, and inversely proportional to [trace] width, of the loop. Using multiple capacitors in parallel, broadside as in the placement shown, reduces component ESL approximately in proportion to count.

In contrast, placing them like a ladder, with the load at one end, does not:

Parallel capacitors in a ladder, modified from https://electronics.stackexchange.com/questions/397647/bulk-capacitor-placement-routing

This way, the ESL from each capacitor, and the traces between them, form a ladder network. The ESL of the others act in parallel with the first, plus strays; the result is less ESL than a single part, but more than with them broadside.


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