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I have some questions about nand memories.

  1. Do we need to erase whole block to rewrite only one page?
  2. If true, what is the algorithm? Cache whole block > edit one page > erase whole block > write whole block?
  3. How random data input works? Do we need erase block to input few bytes in random mode???

p.s. I am writing MSD application with STM32F207ZG mcu + K9F1G08U0B nand

EDIT For newbies like me

How NAND flash works:

We can perform read and write on page basis or use random input or random output in any page. Nothing special about reading, but i hear that reading, like writing, may wear pages.

After erase all bits in erased area is set to 1, and when we write, we only set some bits to 0. Once bit is set to 0, it cannt be set to 1 again, setting bit to 1 is possible only by erasing region containing that bit. As consequence, if we need to fill some region with 0x00, we do not need to erase this region.

And note: Erase can be performed only on block (not page) basis. I found, that when you specify page address to erase, block containing that page will be erased. So we need to specify not a block number to erase, but for example number of first page in block.

Hope this information is correct and will be helpful for someone. Sorry for my broken english ;)

Thanks to supercat for explanation.

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  • \$\begingroup\$ Not all devices allow arbitrary rewriting of ones to zeroes. It's been awhile since I've looked at NAND flash data sheets, but the ones I'm used to limited the number of distinct write cycles that could occur to a page between erasures. I think each data area was allowed one write and each tag area two. It would have been helpful if the spec would allow a sector to be zeroed out even after it was written, but and perhaps such a thing would have worked, but nothing in the spec would justify it. \$\endgroup\$ – supercat Apr 17 '13 at 16:26
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If interoperability with other systems is not required, your choice of algorithms will depend upon the resources you have available (most notably RAM) and your usage patterns. If you can get by with block-level granularity, and if no block will have to be rewritten too many times, the simplest approach is to simply map logical pages directly onto fixed physical blocks. Some applications are amenable to such an approach, but others are not. Generally, what is done is to have logical page addresses and keep a table of where each page is presently stored on the chip. When a page should be changed, a new blank location is selected for it, the data is written there, the location table is updated, and the old page is invalidated. If after such operation a block contains many invalid pages and no valid ones, erase it. If the number of blank pages gets low, the system should identify a block which contains many invalid pages and, move the still-valid pages to new locations in other blocks, and invalidate the copies in the old locations; once that is done, the block won't contain any valid pages anymore and may thus be erased.

There are many variations to this approach based upon things like the amount of RAM available for page tables, the amount of time one is willing to spend searching for pages, etc. If the number of pages is too large to keep a full table in memory, it may be necessary to store some of the table in flash. If this is done, it may be helpful to have a virtual mapping between logical block numbers and physical blocks, and have the "cleanup" operation find a new blank block, copy all of the valid pages from the old block to the corresponding pages in the new one, and assign the new block the same logical block number that the old one had. If one does this, one can avoid updating the tables that hold the locations of pages within the block.

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  • \$\begingroup\$ For a RAM limited system would a simple algorithm be the following: 1. Write out the page and check if there is an error. 2. Check the status of write. If status failed erase block and do step1 else if passed exit \$\endgroup\$ – mindentropy Mar 16 '15 at 10:32
  • \$\begingroup\$ @mindentropy: Whether an approach is acceptable depends upon whether it will exceed the chip's endurance threshold, and whether it will at all times maintain the system in an acceptable state. If a chip allows atomic byte writes that can be relied upon, even when power fails, to either do nothing or succeed fully, it's possible to implement a robust system that avoid leaving anything in a corrupt state. A simple approach like you're describing could have trouble if power is lost during an erase cycle. Note that unlike some older EEPROM devices where even an interrupted erase cycle... \$\endgroup\$ – supercat Mar 16 '15 at 19:06
  • \$\begingroup\$ ...would never cause a non-blank byte to be programmed, many flash devices program all bits in the array prior to erasure (applying erase voltage to an already-blank cell would cause excessive wear). If power is lost during a block erase, one should be prepared to have each attempt to read a byte from that block arbitrarily yield any value from 0-255, independent of what was read on any other attempt. \$\endgroup\$ – supercat Mar 16 '15 at 19:10

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