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I'm trying to simulate JK flip-flop behavior. Everything seems to be working perfectly except that the Q output is not toggling, but Q̅ does when both J and K are up.

My circuit: enter image description here

The result of the simulation: enter image description here

Where does the problem come from?

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  • \$\begingroup\$ Can you explain what the output and input node labels are there for? Why do the inputs have "VCC" associated with them? \$\endgroup\$
    – Andy aka
    Feb 4, 2023 at 11:07
  • \$\begingroup\$ I am unable to answer your question, actually I never thought of it and I couldn't find any explanations of the internet. I always leave it as it is (stupidly). @Andyaka \$\endgroup\$
    – Hibou
    Feb 4, 2023 at 11:14
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    \$\begingroup\$ I don't know why they insist on keeping schematics input on Quartus, which is a synthesis tool. You could describe the same circuit in HDL and specify whichever delay you want to simulate and perform this simulation. If you synthesize this to an actual device (e.g. FPGA) you could also simulate the timing behavior of the final circuit, which could possibly don't even have actual NAND gates. For learning purposes you could use Antonio51's approach or lower one level, implement the NAND gates using transistors and use any SPICE program. \$\endgroup\$
    – devnull
    Feb 4, 2023 at 13:36

1 Answer 1

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This circuit should be considered as a 3 inputs + 2 feedback inputs, and 2 outputs, FSM.
If your gates don't have delays, all could happen.

enter image description here

With a little zoom on an area ...

enter image description here

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  • \$\begingroup\$ Does Quartus take in consideration those delays ? @Antonio51 \$\endgroup\$
    – Hibou
    Feb 4, 2023 at 12:49
  • \$\begingroup\$ Don't know Quartus. \$\endgroup\$
    – Antonio51
    Feb 4, 2023 at 12:54
  • \$\begingroup\$ Made with microcap v12. www.spectrum-soft.com \$\endgroup\$
    – Antonio51
    Feb 4, 2023 at 12:55

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