I have designed a switch-mode power stage with voltage-mode control that uses an LCLC filter in its output to obtain a very low ripple output voltage.

I have empirically arrived at a compensation network that makes its control stable and provides a satisfying bandwith. I now want to carry out a proper small-signal stability analysis with this stable configuration as a starting point. The reason is that different values for the L and C can make it unstable again, so I want to simulate quickly how to adjust the compensation network.

For this I have replaced the comparator with an op-amp and abstracted all the feedback paths as voltage sources (E1 and E2). The signal phout1 is the voltage after the first LC and out1 is the voltage after the second LC. The signal input is provided by V6 (also has a 2.5 VDC bias). This works very well to reproduce the transient behavior of the actual switch-mode circuit.

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I am interested in the gain and phase vs. frequency Bode plots, in a way that takes into account the lowpassing effect that appears when feeding the setpoint from V6 and R5.


Below is shown what I tried. I found out that this method is equivalent to the so called "Middlebrook" method, i.e. it gives identical results. The examples by LTspice itself (e.g. Loopgain2.asc) also produce equivalent results.

I cut the AC feedback to the noninverting input and AC-ground it instead. Then I feed an AC 1 source into one of the op-amp inputs and monitor what arrives on the other end of the cut.

This is shown below. It produces a result that indicates that phase drops to 0 at about 2 kHz with 80 dB of gain left. The transient is fully stable in this case with Rfb=1Meg, but the input signal is also heavily low-passed, so maybe this is what makes it look stable. Does the low-pass simply prevent the destabilizing frequencies from ever occuring on the feedback node?

I tested the latter, by injecting my transient signal into V3 instead of V6. And indeed, it is now oscillating at frequencies that make sense in the context of the loop gain analysis.

That means, that the open-loop gain is correctly measured, but it doesn't take into account the stabilizing lowpass that signals experience when fed from V6 and R5.

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  • \$\begingroup\$ Question has been significantly updated. Earlier comments are now obsolete, but can be seen in this chatroom. [Edited by a moderator to clarify the contents of the chatroom.] \$\endgroup\$
    – tobalt
    Feb 6 at 9:59
  • \$\begingroup\$ @tobalt, I have difficulty to understand your model. What is the topology for the power stage, I think you did not disclose it. Then, why don't you use an averaged model, mine were ported to LTspice long ago and they toggle between CCM and DCM. Finally, you could give a try to my free SIMPLIS templates, they are easy to tweak for reflecting your particular configuration. \$\endgroup\$ Feb 6 at 11:01
  • \$\begingroup\$ @VerbalKint The output stage is a simple synchronous buck, i.e. CCM always. It switches at approx. 1 MHz. Not sure what an averaged model is.. Isn't mine one ? \$\endgroup\$
    – tobalt
    Feb 6 at 11:07
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    \$\begingroup\$ I don't know if this helps, but LTspice released a new milestone version (17.1.x) within the past month which includes a new .fra directive to be used with the new FRA symbol to do these types of analyses directly. \$\endgroup\$
    – Ste Kulov
    Feb 8 at 4:57
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    \$\begingroup\$ @SteKulov indeed missed/forgot this comment.. Do you wanna convert it to an answer ? It pretty much solves this issue..There are two negative feedback paths (one DC+AC, one only AC) So I might have to experiment a bit.. If you have a suggestion in this regard, it would be welcome, too. \$\endgroup\$
    – tobalt
    Apr 7 at 20:18


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