Oscillations at primary side switching node of half-bridge converter

Question

I am designing a 84 W battery charger half-bridge converter from an AC source of 220 - 240 VAC. I am using an SG3525A for the design. From a simulation I did in LTspice, there are some oscillations at the primary side switching node (where both MOSFETs are connected together) at the time when both transistors should be OFF. The oscillations are there even if I add a dead-time resistor. I have attached the image of the schematic of the circuit I am using below:

The drain-to-source voltage waveforms of the highside MOSFET (green) and lowside MOSFET (blue):

I have placed an RC snubber circuit (200 pF capacitor and 9.5 kΩ resistor across the primary transformer winding) but the oscillations are only slightly damped. If I increase the capacitor and reduce the resistor, the oscillations are damped further, but at the expense of higher power dissipation in the resistor.

1. How do I efficiently damp these oscillations without affecting efficiency too much? (The leakage inductance of the primary side with the secondary windings shorted is 20 μH. The primary inductance is 11.26 mH and the secondary inductance is 470 μH).

2. Can these oscillations cause shoot through in the MOSFETs?

The drain current waveforms of the highside MOSFET (green) and lowside (blue):

From my calculations, the peak current of the primary side switch should be about 1.1 A.

3. The high-side MOSFET's gate drive voltage also shows some spikes when in the low state and this spikes reach up to 4.5 V. How can I damp these spikes? Since they can lead to false turn-on of the MOSFET.

The gate to source voltage of the highside MOSFET is:

4. Also, the gate drive voltage has been reduced from 12 V to slightly less than 10 V. I assume it's because the turn off spike goes to below ground. Kindly explain to me how I can avoid the ringing and prevent the voltage from being clamped?

The gate voltage is in blue, the source voltage is in red and the gate to source voltage is in green:

Answer 1

How do I efficiently damp this oscillations without affecting efficiency too much?

You don't need to do anything. When both MOSFETs are off, the residual energy left in the primary oscillates due to leakage inductance and MOSFET drain-source capacitance. It won't hurt anything.

Can this oscillations cause shoot through in the MOSFETs?

No, it can't.

The highside MOSFET's gate drive voltage also shows some spikes when in the low state and this spikes reach up to 4.5 V. How can I damp this spikes?

The source is wobbling up and down and, therefore you want the gate to wobble up and down at the same amplitude and phase. This guarantees that the actual gate-source voltage is OFF and stable (which is what you want).

Kindly explain to me how I can avoid the ringing and prevent the voltage from being clamped?

It doesn't need any fixing --> just look at the gate-source voltage differentially to convince yourself about this.

Answer 2

Sure the ringing is not a real disaster. What I have done is lapped up the ringing by ballparking the dead time to be half a ring period .Practical ring half periods are usually less than 1 microsecond with barefoot powermosfets.I nipped it up on the scope in the last century. You could nowdays use the simulater.You should get a nice clean DS voltage waveform and cool temperatures.Clean wave implies fewer EMC issues down the track.If you need to control operating point which is usually the case controlling the on time will suffice .