I have an H-bridge configuration using gate drivers and bootstrap capacitors to drive the high side MOSFETs. I have a load that I pulse with stored energy from a capacitor. The capacitor voltage is typically 300 V. When I test with a resistor as load (5.2 Ω) my high and low side MOSFETs, in that direction, fail short. However when testing with the inductive load (1.06 Ω, 7.5 mH) there are no issues whatsoever and the H-bridge will pulse the load as many times as asked in whichever direction is desired.

I would have thought that the resistive load would have been an easier switching/pulsing test of the H-bridge since there is no inductive flyback. But maybe the dV/dt of such a sharp turn on/off of the MOSFET is causing avalanche break down of the MOSFETs. Whereas in the inductive load there is a "slope" to the current.

However I do turn off the current abruptly in the inductive load and I would have thought that would be much more stressing to the H-bridge than turning off a resistive load. But maybe that flyback energy/voltage is routed through the opposite body diode so it's not as stressful to the forward conducting MOSFET?

Drivers: Si8230BD
Bootstrap diodes: SARS01

H-bridge schematic:

H bridge schematic 2

Layout: Layout

CH1: yellow, Q6 VGS, 200 V/div
CH2: purple, Q7 VGS, 10 V/div
CH3: cyan, load current, 100 A/div
CH4: green = Q5 VGS, 10 V/div

First pulse of 30 ms left Q5 and Q6 failed short with the resistor as load:

enter image description here


O scope of 30ms pulse with resistors as load

Inductive (actuator) load, after many similar pulses of 30 ms (CH1 corrected to 10 V/div):

O scope with actuator as load

After looking at the photos, I think the ringing is being kicked off by the TVS diodes, but it seems to only happen when the load is resistive. When I remove the TVS diodes the H-bridge is able to handle the resistive load.

Adjustments after answer provided by TimWilliams:

enter image description here

1)bypass cap in parallel with bootstrap

2)use fast recovery diode instead of SARs01

3)I wanted to also add a fast turn off path I have seen suggested in Mosfet driving application guides so that's where the PMEG4005EPK came from.

4)changing TVS connection and part number

question on bullet 4: I believe I understood what you were suggesting with splitting the two resistors and having the TVS connection land in between them. And that setting VGS(on), protecting against outside transients, and protection of gate driver against MOSFET failure, should be done this way. But does adding the fast turn off path with the diode in bullet 3 mess with this intention?

  • 3
    \$\begingroup\$ Please provide schematic, layout (screenshots and photos), and oscilloscope waveforms of all conditions you can. \$\endgroup\$ Feb 8 at 12:58
  • 2
    \$\begingroup\$ What switching frequency are you using? What transistors etc.? \$\endgroup\$
    – Andy aka
    Feb 8 at 13:29
  • 2
    \$\begingroup\$ Is that Si8230BD? It's not a bootstrap driver, it's fully isolated; do you have external supplies? Or if using the bootstrap circuit, please show on the schematic. Layout is still needed. Why such large gate resistors? Why TVS? Without a gate damping resistor, the TVS capacitance most likely causes oscillation; whether this is your problem is not clear at this time. \$\endgroup\$ Feb 13 at 19:35
  • 3
    \$\begingroup\$ @Erv these issues are solved by layout! \$\endgroup\$ Feb 13 at 21:26
  • 2
    \$\begingroup\$ @PStechPaul Those are Altium class/rule markers; I assume a net class for clearance or something like that. Erv: The added schematic is missing a connection between Cap- and GND or PGND; and why are GND and PGND different (and Cap-) at all, can you explain a bit more about that? Or show the complete schematics to the project/system? \$\endgroup\$ Feb 14 at 2:46

1 Answer 1


While it's still not clear what exactly is going on, three significant mistakes are apparent:

  1. Placing a low impedance at the MOSFET gates (G-S);
  2. The layout is worse than Swiss cheese;
  3. The bootstrap diodes are incorrect type.

Minor errors include: no high-frequency bypass with C37 / C44; three different grounds on the schematic (evidently all identical on the PCB); R67-R68 are not labeled; series resistors used inexplicably (not an error, more just odd); no local bypass at the H-bridge; C33, C35, C40, C42 not doing anything; and probably other things but we're down into niggles and pedantry at this point.

The good news then, I guess, is that the basic skeleton is fine! There's logic inputs (assumed), logic power, an isolation gap (well, sort of... the net connected to U18-10 comes quite close to 5V, but all the traces under the isolators can be pushed to the other side for full creepage/clearance); there's a, well this isn't shown by the schematic (or what code if applicable) but the initial pulse appears to be bootstrap charging which is correct; the main output traces/pours have good area (though maybe not great, if we're talking pulses over 100 A here?); etc.

Also, speaking of code (or whatever the logic signal source is), the dead time is set suspiciously low on these drivers (~70 ns), yet the gate resistors are absolutely massive (giving a time constant of ~16 µs!). Worst-case input signals could cause shoot-through of comparable duration (i.e., because one is still turning off while the other is turning on). I'm assuming this is handled by the signal generation, implementing additional dead time externally. (The driver isn't capable of such long dead times anyway, so this is a necessary solution, given the gate resistors as shown.)

So about those mistakes:

1. Low gate impedance

Often, this creates a tuned-gate oscillator, between CDG and CGS, and the inductance of the loop (including the unavoidable lead inductance of the package itself -- for a TO-264, ballpark 10 nH). The TVS diode has about 300-600 pF, and itself around 10 nH inductance. These reactances are series resonant at ~50 MHz, a plausible oscillation frequency (modern designs of Si power switching MOSFETs can support parasitic oscillations up to 400 MHz!). It's possible that, zoomed in far enough, you'd have seen a frequency around here; or it might be lower, dictated by layout strays (the ponderously large loop over to the driver; but the large gate resistor(s) rather isolate this path from the gate itself, so this is somewhat less likely).

Aside: where do these inductance figures come from?

Stray inductance can be eyeballed, as it is proportional to length, inversely proportional to cross section (irrelevant here with flat, widely spaced conductors; wide conductors over a ground plane, however, benefit greatly from trace width), and times a geometry factor (which we can hand-wave as 1 for starters). 1 nH per mm of trace or component lead length is a good rule of thumb.

High frequencies follow the path of least impedance: the closest inside path around the conductive loop. For loose traces on a PCB and no ground plane, the shortest path is along the facing edges of the traces. A circular trace for example follows the inside edge. So the width aspect would be in the copper-thickness axis, but that dimension is minuscule (10s of µm), hence the width effect is fairly irrelevant. With broadside-facing (overlapping) traces and planes, however, the closest path is that facing area, so the width is the trace width as drawn, and currents follow the path (search "pcb image current").

2. Worse than Swiss cheese

It's "worse" because the wide spaces between traces means any EM fields can pass right between them, meanwhile inducing significant voltages into the widely spaced loops, including signal loops such as the logic inputs and gate drive (G-S) loops. Or vice-versa, the currents in these loops induce voltages in nearby loops, and/or radiate to space. There is no meaningful analysis of such a design: every loop couples to every other, whether by mutual EM fields, or by shared current paths (like the two low-side drivers being returned through the same Cap- trace instead of directly to their respective MOSFETs).

If we fill the entire board with an inner layer ground plane (most likely GND on the left, Cap- on the right), EM fields are shunted against the plane, and loop paths suddenly become much shorter: internal fields stay largely within the board, and external fields interact considerably less.

I would still prefer relaying the whole circuit of course, but it has been done as a stopgap measure, adding plane(s) to an existing design and having that pass EMC testing.

(To be clear, this schematic is perfectly fine to do on a two-layer PCB; the components can just be placed a bit closer, probably a few turned around, and the traces brought in closer to respect their current loops. A Cap- ground plane might not even be needed, since the local paths can be fairly distant, and the circuit is simple.)

Incidentally, the reason this mistake is not listed as #1 is because of the very slow gate drive (also the observation that removing TVSs helps). It should be difficult for output dV/dt and dI/dt to be too much of a problem, at least, assuming the Cap- trace loops around just offscreen, and a capacitor is there. This is typically the highest priority for SMPS circuits, which do not have the luxury of such exorbitant switching times.

3. Bootstrap diodes

Aside from the unfortunate name, the SARS01 diodes are, apparently, intentionally slow types. Like, specified as bad or worse than 1N4007. They're also much more expensive (which further explains why I hadn't before noticed their existence). Why so bad? They're intended for a specific application (flyback snubber), where the slow recovery can be somewhat of a feature (for example, Power Integrations makes several flyback regulators for which they recommend a 1N4007 in this position). It's a parts optimization step; equivalent effect can be had with an R+C snubber (albeit probably at higher total losses, but also well controlled because you can choose the R and C; whereas the diode, you're stuck with one kind, no adjustment). Anyway, this is just background, not very relevant here.

In this application however, the problem is that bootstrap charging current may still be flowing when the high side switches on (or for inductive load, when the low side switches off). That puts full recovery loss in the diode, and R67/R68, and may interrupt the high side supply as well (since only a modest-impedance electrolytic* is connected there).

*Or maybe they're polymer or tantalum; lacking BOM info, a wide range of ESR is possible.

Simply substituting with UF4004 or US1J would be fine here.

4. On gate protection

(I didn't tell you there'd be a part 4!)

There's no obvious reason to expect excessive VGS here: the drivers are supplied from stable DC (assumption); the bootstrap should work, well -- layout notwithstanding, but with that fixed, it'll work fine; and the only remaining source is transistor breakdown itself, which I'm afraid isn't going to be mitigated by one puny TVS. (When MOSFETs fail, typically they go three-way short; some VDS gets dumped onto the gate, typically nuking the driver(s).*)

*I even had one combo bootstrap driver / SMPS controller fail so badly that it took out its feedback optoisolator. Just random arcing between its pins, I guess!

Another use-case might be with a gate drive transformer, where the inductance of the transformer, or transient conditions during startup, can lead to peak voltages higher than the intended VGS(on). There are also cases where a zener diode is used to get more precise (and quicker stabilized) drive voltage ("DC restore" circuit).

There are also linear amplifier applications, where VGS(on) needs to be limited as part of the control scheme, or transiently, especially in event of output short-circuit, or perhaps ESD, for example.

In either case -- setting VGS(on), protecting against outside transients, and protection of gate driver against MOSFET failure, should be done this way:


simulate this circuit – Schematic created using CircuitLab

I've used this a few times, to protect the controller/driver against MOSFET failures during development; simply split the drive resistor in half, and put a suitable TVS there (SMAJ12A would be a typical part, but the SA15, or P6KE or etc. would be fine in THT, and of course choose the voltage and uni/bidirectional type appropriate for the application). R2 is likely to be blown open by MOSFET failure, but the driver remains functional. Note this increases switching time somewhat, because of the TVS capacitance.

In several applications (like with a "DC restore" network), R1 may be part of the drive network already (as any general impedance), so isn't needed explicitly. It is needed to protect a driver, so that the TVS's Vpk can be met while limiting current backflowing to the driver.

In any case, the important part is to just have some resistance between TVS and gate. For large transistors like FDL100N50F, it could be just a few ohms; it can also often be a ferrite bead, especially for smaller types, and where speed is required.

A ferrite bead on the TVS lead could also be used, but this will increase the peak clamping voltage depending on rate of transient. So it's better to have it in series with the gate. (So, a slightly bigger bead to slip over the TO-264 gate lead, eh?)

  • \$\begingroup\$ +1 except last paragraph. The bead (or resistor, doesn't really matter) will increase the clamping Vgs in any place you put it. \$\endgroup\$
    – tobalt
    Feb 15 at 5:10
  • \$\begingroup\$ @tobalt With respect to external interference from the driver side, to the gate, or from the gate to the driver, it is correct. Any resistance will increase the clamping from gate to itself, or driver to itself, but clearly the former is untenable as it results in oscillation, and the latter probably won't protect the driver from a fault. (Also, would the internal gate resistance be relevant to such a situation?) \$\endgroup\$ Feb 15 at 6:32
  • \$\begingroup\$ I didn't mean to disagree on the additional resistor as a solution per se. Just saying that its position doesn't really affect by how much the Vgs clamp is increased. And that increase is usually unproblematic anyway. \$\endgroup\$
    – tobalt
    Feb 15 at 6:45
  • \$\begingroup\$ Hmm, so you mean as "strictly increases"? If you mean in the transfer case (limiting peak from driver to gate, or vice versa), I'm still not sure how that would be true? \$\endgroup\$ Feb 15 at 6:49
  • \$\begingroup\$ Ah I see. Well I didn't consider that case given there are already very large resistor in that path. I considered gate-zener oscillation and reverse transfer from the FET. \$\endgroup\$
    – tobalt
    Feb 15 at 8:11

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.