The 1st answer states accurately the impedance shape of two equivalent circuits of C-large in parallel with C-small. It does not tell the whole story.
Why are extra caps added so close to the module if there are more caps inside?
Short Answer: Distributed egress shunts to avoid DC loop inductance resonance getting into analog supply VDDA or designer oversight? I would expect the designer to validate their 2nH choice, so an oversight is unlikely.
The real issue is that the digital current from CMOS noise sources internal filter can resonate in series with the loop path inductance for Vdd3V3 & Gnd. The Clarge internal has some low ESR in mohms in series with L external traces to its source C and thus amplify by the Q or impedance ratio at that resonant frequency.
To fully understand it is critical to simulate and model the lumped elements of the entire system. All traces have a known inductance and 2nH is in the range of only a few mm. The ESR of the caps must be kept ultra low for attenuation yet it also creates a problem with shared voltages with series noise spectrum resonance of the CMOS getting back to the VddA analog channel when the trace is long and the resonance falls in a band where noise spectrum may be high such as 30 MHz.
What are the requirements?
If 12 bit ADC has a Vref = 1.1V then 1 bit= 1.1/4096 = 269 uV. So something in this range or less would be reasonable.
But if the impedance of the Ltrace & Clarge , say 10nH and 10nF is 1 Ohm at 16 MHz with an ESR of the loop at 10 mohms then there is a gain of about 40 dB with no load. These added distributed caps help to load this series LC which now appears as a parallel LC higher impedance reverse path to the DC source.
The logic supply has this “pi” filter is bidirectional so what is the most important direction to analyze the reason I examined the reverse path of noise of the module with lots of CMOS logic noise and very sensitive ADC with a separate.
These current and impedance specs are hard to come by for uC, SoC’s modules, boards and systems. I find the best approach is to model the RLC of every trace and lump them or simplify for the desired attenuation in your design. Then verify your design with a test using the best methods you have such as a calibration routine or a network analyzer to test pads with a DC isolation cap.
The end result is multiple resonances but the goal is to add attenuation of digital load noise from getting back into the ADC ground or the 1.1V derived from the 3.3V VDDA/3 as a reference.
Be sure that you understand the impact of logic noise on ADC’s in a system with shared supplies and filters and be sure to include a ramp test in your system test for linearity, noise and missing codes. Self-generated logic noise on the analog Vref and comparator noise for the SAR cannot be ignored. Try to model or measure, the impedance of your regulator and the noise generated from each load. The sample and hold filter time and comparator response time are important factors for sensitivity to spectral noise. This must be tested and verified to meet your desired noise floor limit.