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I am currently in the process of designing a high-precision mixed signal PCB. I do have some experience designing simpler PCBs, and I have been doing my own research for this question. However I figured it might be better to collect input from people no doubt much more experienced than I am.

Context: I have a mixed digital/analog circuit, with my priority being keeping the analog signals as noise free as possible (its some DAC and ADC stuff where I am dealing with very very low voltages and I need to maintain a high degree of precision). I took the liberty of attaching a very rough functional block diagram to illustrate. It is also important to note that I am not dealing with any RF, high-speed digital signals or anything of the sort.

The entire board will be powered via +5V USB, which will feed directly (and interface with) a microcontroller and some other logic. enter image description here The Problem: The analog section of the circuit requires ±15V, which I obtain with a dual output boost converter. I would like to maintain a level of electrical isolation between the USB side and the boost converter side. I understand I can't have complete isolation since both sections do share the same power supply.

My first instinct was to look into dedicated isolation ICs, and I have settled on a design where I isolate the +5V line with a SN6505 based isolation circuit (which funnily enough uses the same boost-converter IC in it's example application from the datasheet). This is represented by ISO1 in the diagram.

Now since I still need to communicate with some digital peripherals from the other side, I will also employ a SPI/digital isolator (probably something from Analog's ADuM line). This is represented by ISO2 in the diagram.

My Questions

  • I am aware that splitting ground planes is very tricky to do, and there's a lot of mixed opinion. I did do research to educate myself more about current loops and return paths, proper layout and the like. Due to the isolation ICs I would not need to cross any traces over the ground cut. Additionally, there is nothing high frequency involved. This leads me to believe that the ground plane cut (indicated by the RED CUT in the diagram) would be a suitable (and not a entirely stupid) approach for this application.

  • If I migrate to a 4-layer board, would 2 different ground plane layers work? For example, suppose I have the stackup: SIGNAL + DGND + AGND + SIGNAL. This way I don't need to split any ground planes. I am unaware of what noise, EMI, and other implications this might have, and I have not been able to find anything substantial online about this kind of stackup (maybe because its a bad idea?).

  • Would it even be necessary to split the ground planes? My main rationale for wanting to split the supplies is to isolate the computer on the USB end from the boost-converter. However, if there is a smarter way to do this then by all means please let me know!

Any suggestions and criticisms for proper/smarter design would be greatly appreciated!

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  • \$\begingroup\$ In my experience, the usual reason to isolate the USB ground is that your device is hooked up to some other power supply that might not share the same ground and thus you're worried about a ground loop. Is that a concern here? What are the ADC/DAC connected to? \$\endgroup\$ Commented Feb 11, 2023 at 2:54
  • \$\begingroup\$ The device is not hooked up to another power supply (all though I did consider that) so that is not a concern. My main concern was protecting the computer from if anything goes wrong on the boost-converter side, such as flyback spikes, shorts, etc... maybe I'm overthinking it. If I were to not isolate anything, would there be a chance of damaging the computer USB port in any scenario? \$\endgroup\$
    – BlueOyster
    Commented Feb 11, 2023 at 3:04
  • \$\begingroup\$ Rather than an isolated 5V converter then boost converter, you might want to consider an isolated multi-rail converter. It would probably end up smaller and more efficient. You might want linear regs on the analog rails to keep them quiet. You still have the issue of capacitive coupling across the converter which requires a capacitor across the two grounds to shunt the switching noise. As for splitting analog and digital grounds - depends on where currents are flowing across your pcb. Being isolated from USB makes the situation much easier. \$\endgroup\$
    – Kartman
    Commented Feb 11, 2023 at 3:11
  • \$\begingroup\$ The main way you would damage a USB port would be to short high voltage to the data pins. Since you don't have any need to have the data pins close to the high voltage side (and your voltage isn't that high), you're not too likely to run into that problem. \$\endgroup\$ Commented Feb 11, 2023 at 3:24
  • \$\begingroup\$ You need to add the returns to your block diagram. And you also should show us a physical representation of the board. A layout with the various layers would be ideal. In these kinds of applications, you want to make sure that the return currents for the high speed digital signals (in one of the return planes) DO NOT flow pass the low level analog part of the circuit. \$\endgroup\$
    – SteveSh
    Commented Feb 12, 2023 at 0:25

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I don't have the ability to comment, so, I'll just make this as an answer..

From talking/learning from people like Dan Beeker or Todd Hubing, 90% of the time when people think they need to split a GND plane they don't. These aren't your average joes, and, are very well respective people within the industry.

When you say very very low voltages for your ADC/DAC stuff, what does that mean? The calculation of whether or not common impedance coupling can/will affect your SNR in a major way is pretty simple. Imagine the two signals of interest sharing a return path (poorly placed and thought out layout),so, the current return plane (GND Plane) which has a resistance of say 2mOhm, and then multiply by the worse case current. Your stuff sounds pretty low current, so, say 500mA. Vcouple = 0.5*0.002 = 1mV.So, there's your WORSE-CASE common coupling. If, you do that calculation and it's still an issue and you can't space your circuits well, then you could isolate your return paths by using a stack up like you've suggested, or, re-do your circuit in a way so you can space them out well, or, galvanically isolate if there's safety concern. Also, the above is for low frequency signals, since, there current return density from a trace cross sectional point of view spreads out and isn't as "controllable", per say when compared to higher freq stuff (50 or 100 kHz or higher). Higher frequency signals have very predictable current returns, since, they follow the path of least impedance (not resistance like it is for low freq stuff).

Go to here: https://www.google.com/search?rlz=1C1SQJL_enCA974CA974&sxsrf=AJOqlzWr0o1XomkRMxiSFyR1FMhVMzYRig:1676156916546&q=todd+hubing+common+impedance+coupling&sa=X&ved=2ahUKEwiyzeSMy479AhWuMjQIHSW4BZMQ7xYoAHoECAgQAQ&biw=1536&bih=746&dpr=1.25#fpstate=ive&vld=cid:cc30d0df,vid:TUS21J5RPE0

Watch the whole thing, but, he answers your question above at 9:50. He essentially reiterates what I've said above but in more detail and examples, and, just better most likely :).

Nothing wrong with the stack up you've provided, that or another variation GND : SIGNAL : SIGNAL : GND is a fine 4 layer stack up. It's GENERALLY better than the traditional one people tend to follow SIGNAL:GND:POWER:SIGNAL. Problem with that one is the signal layer on layer 4 is orphaned, what it is it referencing? That question is loaded because technically you can reference a power plane, but, still.. Can you make this stack up work, absolutely. You just have to be more mindful. In engineering there are no absolutes and it's always give and take.

A comment I will say about that stack up though is be mindful of your boost converter and what layer it's referencing as a current return. There are certain di/dt loops you want to be a small as possible to reduce your circuits ability to radiate and also it's ability to be immune to outside noise sources. I'm not really sure what you are calling Layer 1, but, if it's the first signal layer you call out, with DGND below it I am assuming you are thinking of using L3 (AGND) as your return path? Not great, since, the z axis path is now through 2 dielectrics (one of the them being the core (the largest dielectric)), so, your loop di/dt loop is now larger, meaning more parasitic inductance = bad (for this case). Now, will your boost work, most likely even using L3, but, depends on your boost and how you are running it.

I think I've blabbed on for long enough, but, that youtube video will answer your questions as well. cheers.

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