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I am simulating a flyback converter working in CCM and I don't understand the results. According to volt-second balance, there's this well-known equation regarding flyback converters:

$$V_{\mathrm{in}}D=nV_{\mathrm{out}}(1-D)$$ where $$n=\frac{N_{\mathrm{pri}}}{N_{\mathrm{sec}}}$$

The application that I'm simulating has following specifications:

$$V_{\mathrm{in}}=77\ \mathrm{V}$$ $$V_{\mathrm{out}}=5\ \mathrm{V}$$ $$I_{\mathrm{out}}=3\ \mathrm{A}$$ $$f_{\mathrm{sw}}=200\ \mathrm{kHz}$$ $$n=11$$

Let's assume that the voltage drop of the diode on the secondary side is about 0.8 V. Therefore the calculated duty cycle is:

$$D=\frac{nV_{\mathrm{out}}}{nV_{\mathrm{out}}+V_{\mathrm{in}}}=0.453$$

The magnetizing inductance is quite big to achieve low ripple current. Also, let's neglect leakage inductance.

$$L_{\mathrm{m}}=L_{\mathrm{pri}}=2420\ \mu\mathrm{H}$$ $$L_{\mathrm{sec}}=\frac{L_{\mathrm{pri}}}{n^2}=20\ \mu\mathrm{H}$$

Here's the LTspice simulation model. I know that I should use a proper controller for the real application but I just wanted to see that the simulation results match with the calculations. As you can see, leakage inductances, snubbers, ESRs and ESLs are neglected; only the essential components are in the simulation model.

Figure of the simulation model

The diode and the transistor are rated high enough to handle the currents and voltages that occur in the circuit.

Here are the output voltage and output current waveforms in a steady-state operation.

LTspice simulation results

The output voltage and current are way too high for some reason that I don't understand. Somehow the calculations don't match with the simulation at all. I would understand if the voltage and current differed for a few percents from the calculations. Is someone able to figure out what's happening in the circuit?

I know that the current is too high because the voltage is too high (Ohm's law). But why is the voltage so high? Any ideas and suggestions are welcome.

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  • \$\begingroup\$ Don't plot V(N003) <-- that is meaningless to anyone reading the question. Use labels. I agree with you duty cycle figure if that's any help. \$\endgroup\$
    – Andy aka
    Commented Feb 11, 2023 at 12:50
  • \$\begingroup\$ The formula for duty is for Dmax. You have to adjust D according to load. D is dependent on load current. \$\endgroup\$ Commented Feb 11, 2023 at 14:14
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    \$\begingroup\$ One-pixel-wide pure blue is also unreadable in the thumbnail, and nearly unreadable full size. \$\endgroup\$ Commented Feb 11, 2023 at 14:44
  • \$\begingroup\$ Jack, in addition to what @Chupacabras said, your FET is simply staying on longer than you think. This is probably because the primary inductor's drain side jumps up in voltage when the FET tries to turn off. And the capacitance between the drain and gate yanks hard on the gate to keep the FET on for a little while longer as that capacitance charges up to the new voltage difference, which takes a little time. So your computed duty cycle won't match the actual duty cycle. Duty cycle adjustment based upon observed output voltage helps fix this issue. Open loop like this, not so much. \$\endgroup\$ Commented Feb 11, 2023 at 19:39
  • \$\begingroup\$ Dear all, thank you for your answers and comments. In the future I'll use node labels. When posting waveforms here, I'll use better colors and thicknesses also. \$\endgroup\$
    – Jackalope
    Commented Feb 13, 2023 at 6:18

1 Answer 1

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The duty cycle equation comes from the fact that once in equilibrium, the \$\Delta\$webers increase during the switch on time equals the \$\Delta\$webers decrease during the switch off time. (Webers are to inductors what charge is to capacitors.)

$$\begin{align*}\frac{D}{f}\cdot V_{_\text{IN}}&=\frac{1-D}{f}\cdot n\cdot V_{_\text{OUT}}\\\\D\cdot V_{_\text{IN}}&=\left(1-D\right)\cdot n\cdot V_{_\text{OUT}}\\\\\therefore\\\\D=\frac{n\,\cdot\, V_{_\text{OUT}}}{n\,\cdot\, V_{_\text{OUT}}+V_{_\text{IN}}}&=\frac1{1+\frac{V_{_\text{IN}}}{n\,\cdot\, V_{_\text{OUT}}}}\end{align*}$$

So I agree with your equation, in theory. (Of course, as you say, the Schottky diode drop must be accounted, as well as the switch and IR drops referred to the secondary.) I don't think you made any mistakes, so far as that goes.

So what's the problem? When the switch (the NFET) turns off, the inductor current will continue to flow into its drain capacitance. The drain voltage will rise only gradually as a result. And only once it has become sufficiently more positive than the supply voltage, will the current be able to "exit" the inductor through the secondary. During most of this time, the drain voltage will be more negative than the supply though, so the primary inductor current will keep rising even with the FET off.

When starting up, the inductor current is still small and that means the current into the drain is lower and therefore it takes longer before the current can flip over to the secondary. So in the first few pulses during startup, I'd expect the current to rise for even longer past the FET turn-off than it will once the steady state is found.

If you were to just use a voltage-controlled switch model, rather than an NFET model, this issue would go away and things would work more as you expected.

Technically, a continuous mode design usually looks at the minimum and maximum current. But the average diode current can be estimated as \$\frac{I_{_\text{LOAD}}}{1-D}=\frac{3\:\text{A}}{1-.453}\approx 5.5\:\text{A}\$.

The Schottky model says that \$R_{_\text{S}}=14.5\:\text{m}\Omega\$, \$I_{_\text{SAT}}=488.73\:\text{nA}\$ and \$\eta=1.0234\$.

So \$V_{_\text{D}}=1.0234\cdot 25.9\:\text{mV}\cdot \ln\left(1+\frac{5.5\:\text{A}}{488.73\:\text{nA}}\right)+5.5\:\text{A}\cdot 14.5\:\text{m}\Omega\approx 510\:\text{mV}\$.

There will be some other likely drops. So let's bump this to \$530\:\text{mV}\$ and call it good. This means the target is \$V_{_\text{OUT}}=5.53\:\text{V}\$. From this I compute \$D\approx 0.44\$. Not that different from your own calculation.

Let's see:

enter image description here

That's pretty close.

I think you have an NFET problem in your circuit.

Let's add the NFET back in and see (N003 is the voltage node for the NFET gate):

enter image description here

Note above the voltage is higher, as you mentioned. But also note that the inductor current keeps rising in magnitude (in the above picture, larger negative values are more towards the bottom there) even after the NFET gate has been turned off? That's the problem. If you plot the drain voltage with one of these transitions, you can see how it rises gradually before the current can flip over to the secondary winding and \$I_{_\text{L1}}\$ becomes zero.

enter image description here

Let's look at what happens at start-up. I mentioned that it would lead to an even more prolonged current increase in the primary. Remember?

enter image description here

You can see that I'm right about that. The first pulse on-period is certainly on longer than the remaining ones. This is because the primary current is smaller, at first, so it will have a harder time charging the drain capacitance initially.

All of the above is why it's important to close the loop by monitoring the output voltage and making duty cycle adjustments (within some allowed range, perhaps) in order to compensate for circuit vagaries.

That's it for now.

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    \$\begingroup\$ @Jackalope also note how much better viewable the trace plots from periplepsis are I recommend you adjust the plot settings if you want to share them here at stackexchange \$\endgroup\$
    – tobalt
    Commented Feb 13, 2023 at 5:59
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    \$\begingroup\$ The mechanism you describe for why the FET remains on too long (Miller feedback) should vanish for zero gate driver impedance. Instead, what is too blame here in my opinion is the FETs output capacitance that makes node VD sink some more current so it can raise its voltage sufficiently to enable the secondary current. \$\endgroup\$
    – tobalt
    Commented Feb 13, 2023 at 6:41
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    \$\begingroup\$ @periblepsis Ok I ammend my prediction 😛 It rises nonlinearly because the output capacitance of the FET is much higher at ~0 Vds than when the drain source voltage has started rising. \$\endgroup\$
    – tobalt
    Commented Feb 13, 2023 at 7:29
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    \$\begingroup\$ @tobalt Ah. I was certain that the behavior had to do with FET capacitance and could be readily fixed using a simple switch. Which it was. So, feel free to edit my answer to improve it. ;) I'm a FET idiot anyway! Keep in mind that whatever you do it must explain why it stays on longer at first (lower voltage across the primary) and much shorter, later on. Better would be a quantitative equation that provides the exact delay once equilibrium is reached, using a datasheet or the model details and the primary inductance. Or, better still, write an answer??? Please? \$\endgroup\$ Commented Feb 13, 2023 at 7:31
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    \$\begingroup\$ @periplepsis A quantitative way would be not a compact form because given the spice model, it would probably involve the integral of a pieceswise Tanh function. If you scroll almost to the end here (ltwiki.org/LTspiceHelp/LTspiceHelp/M_MOSFET.htm) you can see the likely C(DS) dependence used in the spice models. \$\endgroup\$
    – tobalt
    Commented Feb 13, 2023 at 7:44

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